Parallel Recursive Sinusoid Synthesizer With Shorter Critical Paths
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Solution Overview
Problem
Existing digital sinusoid generators face limitations in achieving higher clock frequencies due to long critical paths in their network diagrams, which restrict the rate at which digital sinusoidal values can be generated.
Innovation Solution
The implementation of a revised network diagram with reduced critical path length using equations that allow for the use of fewer digital multiplier and summing elements, enabling higher clock frequencies, and the replication of core recursions to generate multiple sinusoidal values simultaneously, along with a scalable architecture and periodic refresh of digital values to mitigate quantization errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the traditional recursive algorithm implementation is used, then the sinusoid generation is accurate, but the critical path length is long which limits the clock frequency
Solution Approach 1:
The patent divides the sinusoid generation process into multiple independent stages, each computing a portion of the nth sinusoidal value. Instead of computing all terms sequentially in a single critical path, the algorithm segments the computation so that multiple stages can operate in parallel, with each stage contributing to the final result. This segmentation reduces the critical path length while maintaining computational accuracy.
Solution Approach 2:
The patent transitions from a sequential single-dimensional computation approach to a multi-dimensional parallel computation architecture. By organizing the recursive algorithm into multiple stages that operate simultaneously across different computational dimensions, the system achieves higher throughput and reduced critical path without sacrificing the mathematical accuracy of the sinusoid generation.
2Speed
If more digital multiplier and summing elements are used to reduce critical path, then the clock frequency increases, but the device complexity and resource usage increase
Solution Approach 1:
The patent merges multiple computational functions into shared hardware resources. The same digital multiplier and summing elements are reused across different stages of the parallel computation, rather than duplicating full sets of computational units for each stage. This resource sharing approach reduces the total number of multipliers and summing elements while still achieving the desired parallel throughput and reduced critical path.
Solution Approach 2:
The computational elements in the patent are designed to be universal and multi-functional. Each digital multiplier and summing element can serve multiple purposes across different computation stages, depending on the control signals and data routing. This universality allows the system to achieve high-speed parallel computation without proportionally increasing the number of physical components.
3Productivity
If parallel computation stages are implemented, then the throughput increases, but the quantization errors accumulate
Solution Approach 1:
The patent implements feedback mechanisms where the outputs of parallel computation stages are monitored and used to correct quantization errors. By feeding back information about computational accuracy and using correction algorithms, the system maintains precision despite the increased throughput from parallel processing. The feedback loop allows real-time adjustment to compensate for errors introduced by multiple parallel computational paths.
Solution Approach 2:
The system performs preliminary computations and error analysis before final output generation. By anticipating potential quantization errors from parallel computation, the architecture pre-calculates correction factors or uses higher-precision intermediate representations that prevent error accumulation. This preliminary action ensures that even though throughput is increased through parallelism, the final results maintain the required precision.
Data Source
AI summary
A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.