Shared Division and Modulo Circuit for Low-Latency Chip Area Savings

The patent combines multiple dedicated division and modulo circuits into a single shared circuit that processes sets of input numbers. The division logic circuit and modulo logic circuit are merged to handle multiple power-of-two related division and modulo operations simultaneously, reducing chip area while maintaining operational reliability through shared resource utilization.

The patent creates a universal logic circuit that can perform both division and modulo operations on multiple input numbers. The single division logic circuit and single modulo logic circuit are designed to handle various input numbers that are power-of-two multiples or fractions, making the circuit multi-functional and applicable to different operations without requiring dedicated circuits for each case.

The patent merges multiple dedicated circuits into a single shared circuit that processes multiple operations in parallel. By combining the division logic circuit and modulo logic circuit to handle sets of input numbers simultaneously, the system reduces the sequential processing latency that would occur with multiple dedicated circuits while maintaining reliability through the robust shared architecture.

The patent enables continuous processing of multiple input numbers through the single division logic circuit and single modulo logic circuit. Instead of having operations wait for dedicated circuits to become available, the shared circuits continuously process sets of input numbers, eliminating idle time and reducing overall latency while maintaining operational reliability.

The patent designs a universal division logic circuit and universal modulo logic circuit that can handle multiple input numbers through parameterized operation. The circuits are configured to process sets of input numbers that are power-of-two multiples or fractions by adjusting operational parameters rather than requiring separate circuit paths, reducing chip area while managing complexity through standardized multi-functional design.

The patent manages device complexity by changing operational parameters of the single shared circuits rather than altering the physical circuit structure. The division logic circuit and modulo logic circuit adjust their operation based on the specific input numbers being processed, using parameter control to handle different power-of-two relationships without increasing physical device complexity.

The patent maintains high processing speed in the single shared circuits by enabling continuous operation on sets of input numbers. The division logic circuit and modulo logic circuit process multiple operations in a continuous pipeline rather than sequentially, eliminating idle cycles and maintaining throughput speed comparable to multiple dedicated circuits while achieving area reduction.

The patent segments the processing of input numbers into manageable sets that can be handled efficiently by the single shared circuits. By dividing the overall processing task into segments of power-of-two related input numbers, the circuits can optimize their operation for each segment, maintaining high processing speed while reducing chip area through shared resource utilization.