PLD Multiplier Mapping with Ternary Carry Chain Regularization
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Solution Overview
Problem
Existing integrated circuits face challenges in efficiently implementing multipliers due to high logic and routing complexity, which hinders area conservation, power efficiency, and resource utilization, especially in machine learning applications.
Innovation Solution
The method involves multiplier regularization by redistributing partial product bits between chains of programmable logic device (PLD) cells, refactoring arithmetic to ternary from binary, and using N:N compression to reduce carry chain length, thereby optimizing the mapping of soft multipliers onto programmable logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multipliers are implemented using conventional binary arithmetic and standard PLD cell assignments, then the implementation is straightforward, but the area and routing complexity increase significantly
Solution Approach 1:
The patent transforms the arithmetic system from binary to ternary representation. By changing the numerical base parameter, partial product bits are redistributed across three carry chains instead of two, which balances the load and reduces overall routing complexity while maintaining implementation feasibility through systematic mapping rules
Solution Approach 2:
The patent divides the multiplier implementation into multiple parallel carry chains (typically three chains in ternary representation). Each chain handles a subset of partial product bits, segmenting the overall computation task. This segmentation reduces the routing burden on any single chain and allows for more efficient area utilization in the PLD
2Speed
If more PLD cells are used to implement multipliers, then computation speed may improve, but area consumption increases
Solution Approach 1:
The patent merges multiple partial product bit computations into shared carry chains. By using ternary representation, three partial product bits can be summed across three chains simultaneously, allowing better resource sharing and reducing the total number of PLD cells needed compared to conventional binary implementations, thereby reducing area while maintaining computation speed
3Use of energy by stationary object
If carry chain length is reduced through N:N compression, then power consumption decreases, but the number of PLD cells required increases
Solution Approach 1:
The patent changes the arithmetic representation from binary to ternary, which fundamentally alters how carry chains are structured. This parameter change enables more efficient compression ratios in N:N compressors, reducing carry chain length and consequently lowering power consumption, while the systematic mapping ensures that the increase in PLD cell count is minimal and justified by the power savings
Data Source
AI summary
A method for implementing a multiplier on a programmable logic device (PLD) is disclosed. Partial product bits of the multiplier are identified and how the partial product bits are to be summed to generate a final product from a multiplier and multiplicand are determined. Chains of PLD cells and cells in the chains of PLD cells for generating and summing the partial product bits are assigned. It is determined whether a bit in an assigned cell in an assigned chain of PLD cells is under-utilized. In response to determining that a bit is under-utilized, the assigning of the chains of PLD cells and cells for generating and summing the partial product bits are changed to improve an overall utilization of the chains of PLD cells and cells in the chains of PLD cells.