Dual Accumulator Downsampling for High-Rate ADC Slope Estimation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Electrical devices, such as microcontrollers, face challenges in processing high sample rates from analog-to-digital converters (ADCs) due to limited processing power, necessitating the need for effective downsampling methods to reduce the number of samples without losing slope estimation capabilities.

Innovation Solution

The implementation of dual accumulators that support downsampling options like cascaded integrator-comb (CIC) filters and linear least-squares estimation (LLSE) of slope and offset, allowing for hardware-independent downsampling and enabling software to process samples at a slower rate with higher resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high sample rates are used from ADCs, then measurement precision and signal processing capability are improved, but processing power requirements and device complexity increase

Engineering Contradiction:
Improvesignal processing capabilityVSAvoidprocessing power requirements
Core Design Contradiction:
Measurement precisionVSPower

Solution Approach 1:

The patent divides the processing of high-rate ADC samples into multiple segments by implementing dual accumulators that operate at different rates. The first accumulator processes samples at the full ADC rate while the second accumulator processes at a lower rate, effectively segmenting the processing load to reduce overall processing power requirements while maintaining measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dual accumulators as intermediary components between the ADC and the processing core. These accumulators act as mediators that buffer and condition the high-rate samples before they reach the processing core, reducing the immediate processing power burden while preserving signal integrity and measurement accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If high sample rates are used from ADCs, then measurement precision and signal processing capability are improved, but device complexity increases

Engineering Contradiction:
Improvesignal processing capabilityVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The processing system is segmented into two distinct accumulator paths with different operating rates. This segmentation allows the device to handle high-rate ADC output without requiring the entire processing chain to operate at maximum speed, thereby reducing overall device complexity while maintaining measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic rate conversion by using two accumulators operating at different clock rates. The first accumulator runs at the full ADC sampling rate while the second operates at a reduced rate, creating a dynamic processing architecture that adapts to the signal processing needs without requiring uniformly high-speed components throughout the device.

Inventive Principle:
Principle #15Dynamics

3Power

If downsampling is applied to reduce sample frequency, then processing power requirements are reduced, but slope estimation capability may be degraded

Engineering Contradiction:
Improveprocessing power requirementsVSAvoidslope estimation capability
Core Design Contradiction:
PowerVSMeasurement precision

Solution Approach 1:

The patent performs preliminary accumulation and signal conditioning in the first accumulator operating at the full ADC rate before downsampling to the second accumulator. This preliminary action preserves the slope information in the accumulated data, allowing accurate slope estimation even after downsampling reduces the processing power requirements.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dual accumulator architecture maintains continuous useful action by ensuring that the first accumulator continuously processes all ADC samples at full rate to preserve slope information, while the second accumulator simultaneously provides downsampled output for lower-power processing. This continuity ensures slope estimation capability is maintained despite downsampling.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20220253091A1Accumulators for reducing frequency of samples and related apparatuses, systems, methods
Publication Date: 2022.08.11 MICROCHIP TECHNOLOGY INC
  • US20220253091A1 patent drawing
  • US20220253091A1 patent drawing
  • US20220253091A1 patent drawing

AI summary

Accumulators for reducing frequency of samples and related apparatuses, systems, and methods are disclosed. An apparatus includes a first accumulator and a second accumulator. The first accumulator provides a first total. The first total corresponds to a sum of a current sample value of an input signal and a previous value of the first total. The second accumulator provides a second total. The second total corresponds to a sum of the first total and a previous value of the second total.