Binary Scalar Product Circuit With Segmented ADC Weight Processing
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Solution Overview
Problem
Existing vector-matrix multipliers in artificial intelligence and machine learning applications face inaccuracies and high energy consumption due to analog vector multiplication, requiring costly and complex digital-to-analog and analog-to-digital converters.
Innovation Solution
A scalar product circuit that computes binary scalar products using memory cells with distinct current intensities for digital computation, eliminating the need for digital-to-analog converters and simplifying analog-to-digital converters with fewer bits, employing memristors and semiconductor switching elements for efficient binary vector multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If analog vector multiplication is used in vector-matrix multipliers, then computational speed is improved, but measurement precision deteriorates due to inaccuracies in analog computation
Solution Approach 1:
The patent segments the weight values into multiple bit sections, where each bit section corresponds to a specific weight range. This segmentation allows the analog computation to be divided into multiple discrete steps, with each step handling a specific bit position. The current intensity in each column line represents a specific bit of the scalar product result, enabling progressive construction of the final binary result through multiple analog-to-digital conversion stages.
Solution Approach 2:
The patent introduces memory cells as intermediary elements between the analog vector-matrix multiplication and the final digital result. These memory cells store weight values and convert analog voltage inputs into controlled current outputs, acting as a bridge that enables precise digital control of the analog computation process. The memory cells with distinct current intensities serve as mediators that translate binary weight values into proportional analog currents.
2Measurement precision
If analog-to-digital converters with high precision are used, then measurement precision is improved, but device complexity increases due to costly and complex converter design
Solution Approach 1:
The patent segments the analog-to-digital conversion process into multiple stages, with each stage handling a specific bit position of the scalar product result. Instead of using a single high-precision converter, the system uses multiple lower-precision converters (3-bit ADCs) that each convert the current intensity for one bit section. This segmentation reduces the complexity and cost of individual converters while maintaining overall computational accuracy.
Solution Approach 2:
The patent uses multiple 3-bit analog-to-digital converters, which provides more conversion capacity than strictly necessary for each individual bit section. This excessive action ensures high precision in each bit conversion while keeping the converter design simple. The redundant precision capacity is distributed across multiple converters rather than concentrated in a single complex converter.
3Adaptability or versatility
If digital-to-analog converters are used to generate voltages proportional to binary input vectors, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the digital-to-analog converter from the system architecture. Instead of converting binary input vectors into analog voltages using a DAC, the system directly uses binary-weighted current sources that generate currents proportional to the binary input values. This extraction removes the complexity of DAC design while maintaining the necessary adaptability for processing binary input vectors in neural network computations.
4Manufacturing precision
If memristors with distinct current intensities are used, then manufacturing precision is improved, but energy consumption increases
Solution Approach 1:
The patent employs periodic action in the sense of systematically cycling through different bit sections and weight ranges in a structured sequence. The computation proceeds through multiple stages, where each stage processes a specific bit position by activating corresponding memory cells and performing analog-to-digital conversion. This periodic, staged approach enables precise weight storage and computation while managing energy consumption through controlled, sequential operation rather than simultaneous activation of all components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces computational inaccuracies, lowers energy consumption, and simplifies converter design, enabling efficient computation of scalar products in large neural networks with improved scalability and cost-effectiveness.
Implementation Method 1
Each of the memory cells is configured in such a way that when the predetermined voltage value is present, the current intensity of the current that is conducted into the column line when the memory cell is in the second memory state is greater, by a multiple, than the current intensity of the current that is conducted into the column line when the memory cell is in the first memory state
Implementation Method 2
The input voltages are applied to the row lines extending in one direction, and result in currents, across the memristors, into the column lines that extend orthogonally thereto
Data Source
AI summary
A scalar product circuit for computing a binary scalar product of an input vector and a weight vector. The scalar product circuit includes one or multiple adders and at least one matrix circuit including memory cells that are arranged in multiple rows and multiple columns in the form of a matrix, each memory cell including a first memory state and a second memory state. Each matrix circuit includes at least one weight range including one or multiple bit sections, the matrix circuit including an analog-to-digital converter and a bit shifting unit connected thereto for each bit section, the column lines of the bit section being connected to the analog-to-digital converter, and a column selection switching element being provided for each column. The bit shifting units are connected to one of the adders, those bit shifting units that are included in a weight range being connected to the same adder.