Matrix Multiplication Error Correction for Fast Low-Power Processors
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Solution Overview
Problem
Modern processors face errors due to increased speed, reduced power consumption, and closer transistor spacing, leading to unreliable computations in matrix multiplication.
Innovation Solution
An error correcting module, either in software or hardware, detects and corrects errors in matrix multiplication by calculating expected and actual sums of matrix elements, determining error location and magnitude, and adjusting computational processes to prevent recurrence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor speed is increased by increasing the frequency of the internal clock, then the processing speed is improved, but errors in the least reliable transistors occur
Solution Approach 1:
The patent applies preliminary action by computing a verification value (sum of all elements in the result matrix) before the matrix multiplication operation completes. This verification value is then compared against the actual result to detect errors before they propagate, allowing the system to operate at higher speeds with acceptable reliability.
Solution Approach 2:
The patent implements feedback by continuously monitoring the computation results through comparison of the verification value against the actual matrix multiplication result. When discrepancies are detected, the system can trigger error correction mechanisms or adjust operating parameters, creating a closed-loop control system that maintains reliability at high speeds.
2Use of energy by moving object
If the power consumption of the processor is decreased, then energy efficiency is improved, but erroneous computation occurs
Solution Approach 1:
The patent computes a verification value in advance that represents the expected sum of all elements in the result matrix. This preliminary computation allows for error detection without requiring additional high-power operations during the main computation, thus maintaining energy efficiency while ensuring computation reliability.
Solution Approach 2:
The system uses feedback by comparing the pre-computed verification value with the actual computation result. This lightweight comparison operation consumes minimal power but effectively detects erroneous computations, allowing the processor to maintain low power consumption without sacrificing reliability.
3Length of moving object
If the distance between transistors is decreased, then the processor size is reduced, but erroneous computation occurs
Solution Approach 1:
The patent applies preliminary action by calculating the verification value (expected sum) before the matrix multiplication completes. This approach allows compact transistor spacing while maintaining reliability, as the error detection mechanism does not require additional physical space beyond the computational logic already present.
Solution Approach 2:
The system implements feedback through comparison of the verification value with the actual result, enabling error detection in compact designs. This feedback mechanism allows the processor to maintain small transistor spacing while correcting computational errors through software or control logic.
4Reliability
If error detection and correction is implemented, then computation reliability is improved, but additional computational overhead is introduced
Solution Approach 1:
The patent extracts the error detection function into a separate verification step that operates independently from the main matrix multiplication logic. By computing the sum of all elements as a separate verification value and comparing it against the result, the system adds minimal overhead while significantly improving reliability.
Solution Approach 2:
The patent uses copying by creating a verification copy of the computation result through the sum calculation. This verification copy (the sum value) is computed separately and used to validate the main result, providing error detection with minimal additional computational complexity.
Data Source
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AI summary
Introduced here is a technique to detect and/or correct errors in computation. The ability to correct errors in computation can increase the speed of the processor, reduce the power consumption of the processor, and reduce the distance between the transistors within the processor because the errors thus generated can be detected and corrected. In one embodiment, an error correcting module, running either in software or in hardware, can detect an error in matrix multiplication, by calculating an expected sum of all elements in the resulting matrix, and an actual sum of all elements in the resulting matrix. When there is a difference between the expected sum and the resulting sum, the error correcting module detects an error. In another embodiment, in addition to detecting the error, the error correcting module can determine the location and the magnitude of the error, thus correcting the erroneous computation.