SDFQ Multiplexer Scan Transistor Sizing for Race-Free Latching
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Solution Overview
Problem
In semiconductor devices, scan flip-flops face a race condition during scan/test operations due to mismatched signal propagation delays between data and scan groups, leading to potential misinterpretation of logical states and incorrect latching.
Innovation Solution
Configuring transistors in the scan group with a smaller channel size compared to the data group creates a choke, ensuring slower signal propagation during scan/test operations, thereby emulating the propagation delay of combinational logic and avoiding race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors in the scan group are configured with the same channel size as the data group, then the device structure is simple and manufacturing is easy, but race conditions occur during scan/test operations due to mismatched signal propagation delays
Solution Approach 1:
The patent applies local quality by configuring transistors in the scan group with a first channel size while transistors in the data group have a second channel size. This differential configuration creates different signal propagation delays tailored to the specific functional requirements of each group, resolving the race condition issue without requiring complete redesign of the entire device structure.
Solution Approach 2:
The patent changes the channel size parameter of transistors between the scan group and data group. By adjusting this physical parameter, the signal propagation delay is modified to achieve proper timing synchronization during scan/test operations, eliminating race conditions while maintaining structural simplicity.
2Reliability
If transistors in the scan group are configured with a smaller channel size to create a choke, then signal propagation delay is increased to prevent race conditions, but the transistor density and device area are affected
Solution Approach 1:
The patent implements local quality by applying the smaller channel size configuration only to transistors in the scan group where it is functionally required, while leaving data group transistors with standard dimensions. This localized approach prevents race conditions in the scan path without unnecessarily increasing the area of the entire device.
Solution Approach 2:
The patent introduces asymmetry by using different channel sizes for transistors in different functional groups. This asymmetric configuration is optimized for the specific timing requirements of scan operations, creating a choke effect where needed while maintaining area efficiency through non-uniform transistor design.
Data Source
AI summary
A semiconductor device has a cell region including active regions that extend in a first direction and in which are formed components of transistors. The transistors of the cell region are arranged to function as a scan insertion D flip flop (SDFQ). The SDFQ includes a multiplexer serially connected at an internal node to a D flip-flop (FF). The transistors of the multiplexer include data transistors for selecting a data input signal, the data transistors having a first channel configuration with a first channel size, and scan transistors of the multiplexer for selecting a scan input signal, the scan transistors having a second channel configuration with a second channel size. The second channel size is smaller than the first channel size.