Ternary Adder Logic Structure With Reduced FPGA Routing Complexity
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Solution Overview
Problem
Integrated circuit devices, particularly programmable logic devices (PLDs) like FPGAs, face challenges in efficiently implementing both binary and ternary arithmetic operations while maintaining the ability to perform logical functions, as existing structures often require additional inputs and complex routing to facilitate ternary addition without increasing die area or the number of local conductors.
Innovation Solution
The proposed logic block structure includes a plurality of logic modules with dedicated adders and lookup tables, where at least one adder has a direct input from another logic module for ternary operations, and a less-than-fully populated matrix of interconnections that allows for programmable connectivity to replicate the functionality of existing logic elements, eliminating the need for multiplexers and conserving die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dedicated adder with direct input from another logic module is added to facilitate ternary arithmetic operations, then ternary addition capability is improved, but device complexity and routing complexity increase
Solution Approach 1:
The logic block is segmented into multiple logic modules (e.g., 52 logic modules in the logic block), each containing dedicated adders and lookup tables. This segmentation allows ternary addition to be performed in a distributed manner across multiple modules, reducing the complexity of any single module's routing while maintaining overall ternary arithmetic capability.
Solution Approach 2:
The logic modules are designed with multi-functionality to perform both binary and ternary arithmetic operations using the same basic structure. The dedicated adders can operate in different modes (binary addition, ternary addition) depending on the configuration, eliminating the need for separate dedicated routing structures for different operation types.
2Adaptability or versatility
If additional inputs are added to logic modules to maintain binary and logical operations while enabling ternary arithmetic, then functionality is improved, but die area increases
Solution Approach 1:
The inputs for binary operations and ternary operations are merged into a unified structure. The logic modules share common input pathways and resources, such that the same physical inputs can be used for both binary logic operations and ternary arithmetic operations, eliminating the need for separate dedicated input structures that would increase die area.
Solution Approach 2:
Each logic module is designed as a universal unit that can perform multiple functions (binary addition, ternary addition, logical operations) using the same set of inputs and resources. This multi-functionality ensures that no additional inputs are required beyond what is needed for the most complex operation, preventing die area expansion.
3Device complexity
If the interconnection matrix is made less-than-fully populated to replicate logic element functionality, then device complexity is reduced, but connectivity options are limited
Solution Approach 1:
The interconnection matrix is designed with local quality variations where specific regions or patterns of connections are optimized for particular functions. Rather than requiring all possible connections, the matrix provides sufficient local connectivity options to replicate logic element functionality while maintaining a less-than-fully populated structure that reduces overall complexity.
Data Source
AI summary
A logic circuit has a first logic element (“LE”) including a first lookup table (“LUT”), where the first LUT is operable to produce a carry from a first set of bits of at least two numbers. The logic circuit also has a second LE including a second LUT, where the second LUT is operable to produce a sum from a second set of bits of the at least two numbers. The second LE also includes an adder coupled directly to the first LUT and coupled to the second LUT, where the adder is operable to add the carry and the sum. The at least two numbers may be three numbers, but the logic circuit includes a set of connections operable to programmably interconnect selected inputs so that the logic circuit is operable to add only two numbers. The logic circuit may be incorporated in a programmable logic device.