Partial Product Multiplier Using Radix-4 Decoding and Tripler Circuitry
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Solution Overview
Problem
Multiplier circuits in integrated circuits, particularly in AI applications, consume significant area and energy resources due to the large number of instances required, and existing decoding methods are complex and inefficient.
Innovation Solution
The use of direct radix 4 decoding and tripler circuitry with decomposed carry prefix trees in multiplier circuits to generate partial products, reducing complexity and resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional multiplication methods are used in integrated circuits, then multiplication functionality is achieved, but area and energy resources are significantly consumed
Solution Approach 1:
The patent segments the multiplication process into partial product generation using decoding circuitry and partial product summation using compressor circuits. This segmentation allows for optimized resource usage by separating the generation and summation functions, reducing overall circuit area while maintaining multiplication efficiency.
Solution Approach 2:
The patent transitions from traditional binary multiplication to radix-4 decoding, effectively changing the dimensional approach by processing 2 bits at a time rather than 1 bit. This dimensional change reduces the number of partial products needed and optimizes the use of compressor circuits, thereby reducing area consumption.
2Productivity
If traditional multiplication methods are used in integrated circuits, then multiplication functionality is achieved, but energy resources are significantly consumed
Solution Approach 1:
By segmenting the multiplication into decoding and compression stages, the patent enables energy-efficient operation. The decoding circuitry generates partial products in parallel, and the compressor circuits sum them efficiently, reducing the overall energy consumption compared to traditional sequential multiplication methods.
Solution Approach 2:
The patent changes the operational parameters by using radix-4 decoding instead of traditional binary multiplication. This parameter change optimizes the balance between speed and energy consumption, achieving higher multiplication efficiency with reduced energy usage through more efficient partial product generation and compression.
3Ease of operation
If complex decoding methods are used, then partial product generation is achieved, but circuit complexity increases
Solution Approach 1:
The patent segments the decoding function into dedicated decoding circuitry that processes 2 bits at a time to generate 2-bit partial products. This segmentation simplifies the overall decoding process by breaking it into manageable units, making the circuit easier to operate while controlling complexity through modular design.
Solution Approach 2:
The decoding circuitry is designed to universally handle all 4 possible 2-bit input combinations (00, 01, 10, 11) and generate corresponding partial products (0, 1× multiplicand, 2× multiplicand, 3× multiplicand). This universal design simplifies operation by providing a single circuit that handles all cases, reducing the need for multiple specialized circuits.
Data Source
AI summary
Integrated circuit devices, methods, and circuitry for an efficient multiplier are provided. Multiplier circuitry to multiply a multiplicand value with a multiplier value may include, among other things, decoding circuitry, tripler circuitry, and partial product multiplexing circuitry. The decoding circuitry may decode bits of the multiplier value using a decoding scheme that includes at least a coding that indicates a triple, the tripler circuitry may generate a triple of the multiplicand value and may include circuitry to generate the triple of the multiplicand value that sums at least two different vectors, and the partial product multiplexing circuitry may select the triple of the multiplicand as a partial product when the coding indicates the triple.