Floating-Point Conversion Circuit Without Exponent Bias Subtraction
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Solution Overview
Problem
Existing binary logic circuits for converting floating point numbers to fixed point numbers are inefficient due to the need to subtract the exponent bias, which slows down the conversion process and increases hardware requirements.
Innovation Solution
A binary logic circuit that shifts the mantissa of a floating point number based on the exponent without subtracting the bias, using a split-path shifter or a single shifter that offsets the exponent to determine the shift value, allowing for conversion of floating point numbers to fixed point numbers for both positive and negative true exponents using a single shifter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the exponent bias is subtracted to determine the shift value, then the conversion accuracy is improved, but the conversion time increases and hardware complexity increases
Solution Approach 1:
The patent extracts only the necessary portion of the exponent information needed for shifting, avoiding the full subtraction operation. By using the exponent field directly or with minimal processing to determine shift amounts, the design removes the time-consuming bias subtraction step while retaining sufficient precision for accurate conversion.
Solution Approach 2:
The patent performs preliminary arrangement of the exponent and mantissa fields during floating-point number formation, such that the shift value can be directly derived from the exponent field without requiring subtraction operations during conversion. This pre-preparation enables faster conversion while maintaining accuracy.
2Measurement precision
If the exponent bias is subtracted to determine the shift value, then the conversion accuracy is improved, but the hardware requirements increase
Solution Approach 1:
The patent extracts only the essential exponent information needed for shifting operations, eliminating the need for complex subtraction circuitry. By directly using the exponent field or simple transformations thereof, the design reduces hardware complexity while preserving conversion accuracy.
Solution Approach 2:
The patent uses copies or direct readings of the exponent field values to determine shift amounts, avoiding the need for complex subtraction circuits. This approach maintains accuracy by preserving the original exponent information while simplifying the hardware required for conversion.
3Device complexity
If a single shifter is used instead of multiple shifters, then the hardware complexity is reduced, but the ability to handle both positive and negative exponents simultaneously is limited
Solution Approach 1:
The patent employs a dynamic single shifter that can adapt its shifting behavior based on the exponent value. By making the shifter's operation conditional and flexible, it can handle both positive and negative exponents sequentially within a single hardware unit, maintaining low complexity while preserving throughput through efficient resource utilization.
Solution Approach 2:
The patent designs a universal shifter that can perform multiple functions - handling both positive and negative exponents, different shift distances, and various conversion scenarios - within a single hardware unit. This multi-functional approach reduces overall hardware complexity while maintaining conversion throughput through versatile resource usage.
Data Source
AI summary
A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1),bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.