3D Cross-Point Memory Array With Merged Bit-Line and Word-Line Etching
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Solution Overview
Problem
Conventional resistance random access memory (ReRAM) devices require a large number of process steps and decoders as the number of stacked layers increases, leading to increased area and complexity in forming three-dimensional memory arrays.
Innovation Solution
The solution involves forming a resistance random access memory device with vertically stacked bit-lines and comb-shaped word-lines that are electrically connected, reducing the number of word-lines and decoders needed by using a single etching process for both bit-line and word-line formation, thereby simplifying the fabrication process and achieving a highly dense memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory layers increases to achieve higher density, then the memory capacity increases, but the number of process steps and decoders increases linearly, leading to increased device complexity and fabrication difficulty
Solution Approach 1:
The patent merges the formation of bit-lines and word-lines into a single etching process. The bit-line stack and comb-shaped word-line are formed simultaneously in one etching step, eliminating the need for separate etching processes for each conductor type. This merging of formation processes directly reduces the total number of process steps while maintaining the ability to form multiple stacked memory layers, thereby resolving the contradiction between increasing memory capacity and reducing device complexity
Solution Approach 2:
The single etching process serves multiple functions: it forms both the bit-line stack and the comb-shaped word-line structure, and it creates the necessary trenches for the resistance memory thin film. This multi-functional approach to the etching process reduces the overall number of fabrication steps required as memory layers are stacked, addressing the contradiction between higher memory capacity and reduced process complexity
2Quantity of substance
If the number of stacked memory layers increases to achieve higher density, then the memory capacity increases, but the area required for decoders increases, leading to reduced integration efficiency
Solution Approach 1:
The patent merges the bit-line and word-line formation into a single etching process, which reduces the total number of decoders needed. By forming the comb-shaped word-line that extends vertically between bit-line stacks, the design reduces the number of separate decoder circuits required compared to conventional approaches, thereby reducing the decoder area while maintaining high memory capacity through multiple stacked layers
3Manufacturing precision
If conventional separate etching processes are used for bit-line and word-line formation, then each conductor can be precisely formed, but the total number of process steps increases, leading to reduced manufacturing efficiency
Solution Approach 1:
The patent combines the etching processes for bit-line and word-line formation into a single etching step. The etching process simultaneously forms the bit-line stack and the comb-shaped word-line structure, reducing the total number of process steps from two separate etching processes to one. This merging maintains manufacturing precision through proper process design while significantly improving productivity by reducing the overall fabrication time and number of steps
Data Source
AI summary
Provided is a resistance random access memory device and a method of fabricating, the same. The method includes forming a bit-line stack in which a plurality of local bit-lines are vertically stacked on a substrate, forming a word-line including a plurality of local word-lines that extend in a vertical direction toward a side of the bit-line stack and a connection line that extends in a horizontal direction to connect the plurality of local word-lines with one another, and forming a resistance memory thin film between the bit-line stack and the word-line. The present inventive concept can realize a highly dense memory array with 3D cross-point architecture by simplified processes.