Solid-State Devices TRIZ Cases

Metal-induced crystallization forms thin polysilicon channels in a semiconductor memory device, reducing crystal grain boundaries and stabilizing the S value.

A curable silicone composition uses a specific organopolysiloxane blend and hydrosilylation catalyst to form a cured product.

Positioning the block word line over the memory block avoids overlapping with the word line group, reducing parasitic capacitance.

Gate-first methodology integrates non-volatile memory with logic transistors using a protective barrier and shared high-k dielectric layer.

Wiring segments on the thin film transistor layer eliminate sensing electrode wirings, reducing dead areas and improving sensing linearity.

A display device uses light-transmitting areas in pixel groups to enable camera integration within the screen.

An anti-spacer process forms sub-resolution semiconductor features by chemically modifying and removing mask material portions.

Organic filling layer replaces rigid inorganic materials to enable dynamic folding of flexible array substrates.

Dummy gate electrodes and sidewall films on SOI substrates block shifted contact plugs from reaching the support substrate, reducing leakage current.

A layered electrode structure integrates sensing and control electrodes within a single display substrate to enable active matrix capacitive fingerprint detection.

Fluorine oxidation stabilizes Mn4+ doped phosphors against high temperature degradation, maintaining luminous efficacy.

A carboxylic acid coating encapsulates manganese-activated complex fluoride phosphor particles to protect them from environmental degradation.

Ridge structures with sloping surfaces position light-transmitting regions to enable dual field display while reducing overall device thickness.

Segmenting frame headers from payload data across separate inter-chip pathways resolves the I/O bottleneck in stacked IC systems.

Direct substrate connections via photosensitive resin eliminate intermediate circuit boards, reducing manufacturing costs and frame width.

A semiconductor light-emitting device incorporates a substrate piercing portion to establish an electrical path connecting to the active layer.

A heterocyclic compound enables delayed fluorescence in organic light-emitting devices through internal charge transfer.

A magnetic memory cell structure segments a continuous soft ferromagnetic storage layer into discrete domains to reduce write current requirements.

Graded germanium concentration in a polycrystalline silicon layer reduces resistivity and prevents metallic film peeling to stabilize capacitor structures.

Electrochemical porosification of n-GaN layers enables hydrogen diffusion from buried p-GaN during annealing, eliminating complex regrowth steps.

A semiconductor body in amorphous or polycrystalline state forms a varactor structure with distinct electrode layers.

A semiconductor memory device stacks control gate electrodes and uses specific via contact positions to reduce wiring lines.

Shifting terminals in column direction reduces space requirements while maintaining adhesive flowability for reliable electrical connections.

A common blue organic electroluminescent layer uses tailored host and dopant materials to prevent electron leakage between color layers.

A functional layer forming ink uses mixed solvents with different boiling points to maintain fluidity during drying.

High-k material and selective metal deposition fill the gate channel, reducing resistance while preventing discontinuation in fin structures.

A barrier structure creates a cavity around an integrated circuit die to exclude underfill material during packaging.

Segmented triangular electrodes determine touch coordinates using fewer wires, reducing short-circuit risks in dense in-cell displays.

Hybrid inkjet printing and spin drying form uniform organic light-emitting device films, resolving solvent evaporation inconsistencies.

Metal dopants in the capping layer scatter light to reduce color cast while maintaining high refractive index for better brightness uniformity.

Vertical reflection repositions the mirror above the chip, resolving size and heat dissipation trade-offs in compact laser modules.

A pixel structure uses micro cavities of different lengths to emit primary colors with distinct wavelengths.

Segmented auxiliary lyophilic patterns create controlled ink accumulation zones that resolve film thickness limitations in narrow pattern printing.

Optimized electrode thickness ratios reduce surface roughness and prevent metallic diffusion during fabrication.

Hollow-core organic particles reduce permittivity below 2.6 to minimize parasitic capacitance between display and touch units.

Non-straight vertical banks minimize ink color mixing and thickness variations during solution processing.

Multi-channel LED strings with independent drive currents generate tunable white light across correlated color temperature ranges.

Vertically stacked bit-lines merge with comb-shaped word-lines via a single etching step to form dense memory arrays.

Supplementary gates at row ends maintain uniform gate lengths across semiconductor integrated circuits.

A composite hole transporting layer balances electron and hole injection to lower driving voltage and extend device lifespan.

Integrating a permalloy sensor atop a planarized semiconductor reduces power consumption and prevents iron contamination in fabrication.

Protruding tips on the auxiliary wiring layer merge conductive functions, eliminating complex patterning steps and contact holes to increase aperture ratio.

An electron adjusting layer with specific ionization potential controls mobility in organic light emitting diodes.

Segmented auxiliary lines reduce capacitive coupling between scan and data lines, preventing grey scale variations in pixel array substrates.

Insulating films segment organic semiconductor layers to block leakage current, enabling high-resolution fingerprint and vascular pattern detection.

A dual gate line array substrate with horizontal common electrode lines positioned to avoid drain overlap in advanced super dimension switch liquid crystal displays.

Absorption enhancement structure with curved sidewalls increases light receiving surface area on image sensor substrates.

Applying a negative electrical bias during annealing reduces oxygen vacancy density, lowering threshold voltage and gate leakage current in high-k transistors.