Semiconductor Memory Block Word Line Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density and performance due to the need for additional space and potential parasitic capacitance issues caused by overlapping block word lines and word lines.
Innovation Solution
The semiconductor memory device design includes a block decoder that outputs block selection signals via a block word line, which is positioned over the memory block to avoid overlapping with the word line group, reducing parasitic capacitance and allowing for a more integrated and efficient layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the block word line is positioned over the memory block to transmit block selection signals, then the integration density is improved, but parasitic capacitance increases due to potential overlapping with the word line group
Solution Approach 1:
The block word line is positioned in the third dimension (over the memory block) rather than in the same plane as the word line group, allowing signal transmission while avoiding parasitic capacitance issues through spatial separation in vertical dimension
Solution Approach 2:
An interlayer insulating layer is introduced as an intermediary between the block word line and the word line group, providing electrical isolation that prevents parasitic capacitance while allowing both conductors to coexist in close proximity for space efficiency
Data Source
AI summary
A semiconductor memory device includes a block decoder configured to output block selection signals for selecting memory blocks in response to a row address signal, a first memory block including a first drain select line, a first source select line, and a first word line group including a plurality of first word lines disposed between the first drain select line and the first source select line, the first memory block disposed between the block decoder and a first switching group, the first switching group configured to transmit first operating voltages to the first memory block in response to a first block selection signal among the block selection signals, and a first block word line configured to transmit the first block selection signal to the first switching group and disposed over the first memory block to avoid overlapping with the first word line group.