Stacked FPGA Configuration via Inter-Chip Address and Data Buses
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Solution Overview
Problem
The interconnection bottleneck in high-performance semiconductor systems, where the increased capacity and speed of logic on ICs like FPGAs are not matched by the number and performance of I/O connections, necessitates innovative IC stacking techniques to effectively configure and interconnect multiple dies.
Innovation Solution
A semiconductor device comprising a field-programmable gate array (FPGA) die with a frame address bus and a second IC die stacked and interconnected via an inter-chip frame address and data bus, utilizing an array of contacts for direct communication and configuration, allowing the second IC die to be addressed and configured like part of the FPGA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If IC die stacking techniques are used to increase I/O connections, then the interconnection bottleneck is addressed, but the device complexity increases
Solution Approach 1:
The configuration interface is segmented into separate functional components: frame address buses for addressing and frame data buses for data transfer. This segmentation allows independent optimization of each bus type and simplifies the overall configuration process by dividing it into address phase and data phase operations.
Solution Approach 2:
A frame structure is introduced as an intermediary mechanism between the FPGA die and the second IC die. The frame includes a frame header with address information and a frame body with data, serving as a standardized communication protocol that mediates the interaction between stacked dies and simplifies the configuration interface.
2Productivity
If direct inter-chip configuration is implemented, then configuration speed is improved, but the inter-chip contact requirements increase
Solution Approach 1:
The configuration interface is divided into separate address and data pathways. The frame address bus carries only addressing information while the frame data bus carries configuration data, allowing parallel operation and reducing the need for every contact to handle both address and data signals simultaneously.
Solution Approach 2:
The configuration process is organized into temporal phases (address phase and data phase) rather than requiring all signals to be present simultaneously. This dimensional separation in the configuration protocol allows for more efficient use of inter-chip contacts over time.
Data Source
AI summary
A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.