NVM Logic Integration Gate-First High-K Metal Gate
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Solution Overview
Problem
The integration of non-volatile memory (NVM) transistors with logic transistors is challenging due to different requirements for charge storage, particularly with high-k gate dielectrics and metal gates, where the unique charge storage layer complicates integration.
Innovation Solution
A method involving the formation of a gate structure for NVM cells with a charge storage layer, using nanocrystals, and a hard mask to create sidewall spacers, while simultaneously performing source/drain implants in both NVM and logic portions, allowing for the integration of metal gate transistors alongside NVM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gates or nanocrystals are used for charge storage in NVM transistors, then charge storage capability is improved, but integration with logic transistors becomes difficult due to unique layer requirements
Solution Approach 1:
The patent extracts the charge storage function from the traditional floating gate structure and implements it using nanocrystals formed within the high-k gate dielectric layer. This separation allows the charge storage mechanism to be integrated within the existing logic transistor gate stack, eliminating the need for separate floating gate layers and enabling co-integration with logic transistors using the same high-k metal gate process
Solution Approach 2:
The high-k gate dielectric layer serves multiple functions: it acts as the gate insulator for logic transistors and simultaneously provides the matrix in which nanocrystals are formed for charge storage in NVM transistors. This multi-functionality allows both logic and memory devices to share the same gate stack structure, simplifying integration
2Reliability
If different charge storage layers are used for NVM transistors, then charge storage is enabled, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the charge storage layer formation with the high-k gate dielectric deposition process. Nanocrystals are formed by depositing a precursor material along with the high-k dielectric, followed by a thermal treatment step that transforms the precursor into nanocrystals. This combined process eliminates separate charge storage layer deposition steps and enables simultaneous fabrication of logic and memory devices using the same process flow
Data Source
AI summary
A method of making a semiconductor device includes forming a split gate memory gate structure on a memory region of a substrate, and protecting the split gate memory gate structure by depositing protective layers over the memory region including the memory gate structure and over a logic region of the substrate. The protective layers include a material that creates a barrier to diffusion of metal. The protective layers are retained over the memory region while forming a logic gate in the logic region. The logic gate includes a high-k dielectric layer and a metal layer. A spacer material is deposited over the logic gate. Spacers are formed on the memory gate structure and the logic gate. The spacer on the logic gate is formed of the spacer material and the spacer on the memory gate structure is formed with one of the protective layers.