Stacked Control Gate Electrodes Via Contact Arrangement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration levels and capacity while maintaining efficient data storage and retrieval, particularly in three-dimensional configurations where wiring complexity and manufacturing costs are concerns.
Innovation Solution
The semiconductor memory device employs a configuration with stacked control gate electrodes and semiconductor layers, utilizing a specific arrangement of via contacts and wiring lines to reduce the number of layers and wiring lines, thereby enhancing integration and reducing manufacturing costs, while maintaining efficient data storage and retrieval capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell configuration is implemented to increase integration level, then storage capacity is improved, but wiring complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional stacked configuration, where memory cells are arranged vertically across multiple layers. Control gate electrodes are stacked in the vertical direction above the substrate, with via contacts connecting to different control gates at different heights, enabling increased storage capacity while managing wiring complexity through systematic spatial organization
Solution Approach 2:
The patent implements a nested structure where via contacts are positioned within or adjacent to memory cell structures, and control gate electrodes are stacked within the vertical space of the memory device. The via contacts connect to control gates that are nested in the vertical stack, creating a compact integrated structure that reduces overall device footprint while maintaining high storage capacity
2Quantity of substance
If three-dimensional memory cell configuration is implemented to increase integration level, then storage capacity is improved, but manufacturing cost increases
Solution Approach 1:
By stacking control gate electrodes and memory cells vertically, the patent achieves higher integration density without proportionally increasing manufacturing complexity. The vertical stacking allows multiple memory cells to share common structures (such as bit lines and source lines), reducing the total number of manufacturing steps and materials required compared to expanding horizontally
Solution Approach 2:
The patent designs the three-dimensional structure so that shared structures serve multiple functions: control gate electrodes serve as both control elements and structural supports, via contacts serve as both electrical connections and structural anchors, and the stacked configuration allows single manufacturing processes to create multiple functional layers simultaneously, thereby reducing overall manufacturing cost
Data Source
AI summary
According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate. The semiconductor memory device further comprises first and second control gate electrodes and third and fourth control gate electrodes stacked sequentially above the substrate and first through fourth via contacts connected to these first through fourth control gate electrodes. The third and fourth control gate electrodes face the first and second control gate electrodes. Positions of the first and second via contacts are far from each other. Positions of the third and fourth via contacts are close to each other.