Semiconductor Integrated Circuit Gate Uniformity
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Solution Overview
Problem
The existing semiconductor integrated circuits face challenges in suppressing non-uniformity in gate lengths due to optical proximity effects, which lead to variations in propagation delay times and require significant process efforts and increased Turn Around Time for corrections, especially when gate lengths and intervals are not standardized.
Innovation Solution
Incorporating two or more supplementary gates, such as dummy gates or inactive transistors, at the ends of each gate row to ensure that active transistors are always accompanied by multiple neighboring gates, allowing for uniform OPC corrections across the semiconductor integrated circuit, thereby maintaining consistent gate lengths and reducing non-uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate lengths and intervals are not standardized, then design flexibility is improved, but non-uniformity in gate lengths due to optical proximity effects increases
Solution Approach 1:
The patent applies preliminary action by pre-defining standardized gate lengths and intervals in the circuit design phase. All gates are designed with lengths from a predetermined set of values and intervals from a predetermined set of values, ensuring that optical proximity effects are uniformly managed across the circuit before fabrication occurs. This standardization eliminates non-uniformity issues while maintaining design flexibility through the use of multiple standardized values.
2Manufacturing precision
If OPC corrections are applied to non-standardized gates, then gate length accuracy is improved, but correction time and process efforts increase
Solution Approach 1:
The patent changes the parameters of gate lengths and intervals to belong to predetermined standardized sets. By constraining gate lengths to specific standardized values and intervals to specific standardized values, the patent reduces the complexity of OPC corrections. This parameter standardization allows for more efficient and uniform OPC processing, reducing both correction time and process efforts while maintaining high gate length accuracy.
3Manufacturing precision
If multiple supplementary gates are added to gate rows, then non-uniformity suppression is improved, but device complexity increases
Solution Approach 1:
The patent applies homogeneity by ensuring that all gates in a gate row follow the same standardized length and interval patterns. By making gate lengths and intervals homogeneous (from predetermined sets), the patent reduces non-uniformity caused by optical proximity effects. The supplementary gates are designed with the same standardized parameters as other gates, creating a homogeneous structure that suppresses non-uniformity without significantly increasing device complexity.
Data Source
AI summary
A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.