3D Signal Delay Line Layout for Compact PCB Footprints
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Solution Overview
Problem
Existing delay line designs for power amplifiers require large sizes to achieve long delays and good delay ripple, making it difficult to realize compact radio products, and often necessitate increased spacing between coaxial lines and additional space for impedance matching, leading to larger PCB footprints.
Innovation Solution
The design incorporates signal electrodes at different heights, introduces holes and grooves to reduce coupling, and includes an impedance matching circuit, reducing the size and insertion loss of the delay line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional delay line designs are used to achieve long delays and good delay ripple, then the signal delay performance is improved, but the device size increases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional structure by stacking multiple signal electrodes at different heights. This vertical arrangement allows the delay line to achieve longer effective electrical length (improving delay performance) without proportionally increasing the PCB footprint area, thus resolving the contradiction between delay performance and device size.
Solution Approach 2:
The patent embeds multiple signal electrodes within a compact vertical space, nesting them at different heights within the same horizontal footprint. This nested arrangement maximizes the use of available space by stacking functional elements vertically, enabling long delay lines to fit within smaller device envelopes while maintaining good delay ripple characteristics.
2Reliability
If increased spacing between coaxial lines is used to reduce coupling, then the delay ripple is improved, but the PCB footprint increases
Solution Approach 1:
Instead of increasing horizontal spacing between signal lines (which would increase PCB footprint), the patent introduces vertical separation by positioning signal electrodes at different heights. This three-dimensional spacing reduces electromagnetic coupling between adjacent signal lines while maintaining a compact PCB footprint, as the coupling reduction is achieved through vertical rather than horizontal separation.
3Reliability
If additional space is allocated for impedance matching circuits, then the signal integrity is improved, but the device size increases
Solution Approach 1:
The patent integrates the impedance matching circuits directly within the delay line structure itself, merging the delay function and impedance matching function into a single unified component. This eliminates the need for separate dedicated space for impedance matching circuits, as they are embedded within the same vertical stacking structure, thereby improving signal integrity without increasing overall device size.
Solution Approach 2:
The delay line structure is designed to perform multiple functions simultaneously: it provides signal delay, maintains impedance matching, and reduces coupling effects. By making the delay line multi-functional, the patent eliminates the need for separate dedicated components for each function, thereby improving signal integrity while keeping the device compact.
Data Source
AI summary
The present disclosure provides a device for signal delay. The device comprises: a frame of insulation material; multiple signal electrodes provided in the frame and electrically connected to each other in series; an input terminal electrically connected to a first of the multiple signal electrodes and configured to receive an input signal; and an output terminal electrically connected to a second of the multiple signal electrodes and configured to output an output signal that is delayed by the multiple signal electrodes with respect to the input signal, wherein at least one of the multiple signal electrodes is located at a different height than those of other signal electrodes with respect to a surface on which the device is to be mounted.