3D Die Side-Wall Interconnects Without TSV Keep-Out Zones
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Solution Overview
Problem
Conventional 3D chip stacks rely on through-silicon vias (TSVs) for interconnections, leading to larger chip sizes and inefficient use of space due to keep-out zones and limitations in placing IP cores.
Innovation Solution
Implementing side wall interconnections between die layers, including side wall pads and RDL layers, which reduce the need for TSVs and allow for more efficient use of space by providing vertical and lateral connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used for interconnections between die layers, then electrical connectivity is achieved, but chip footprint area increases due to keep-out zones
Solution Approach 1:
The patent transitions from vertical TSV interconnections to lateral side-wall interconnections. By forming conductive structures on the side walls of through-holes rather than filling the through-holes completely, the interconnection moves to a different dimensional configuration that reduces the keep-out zone footprint while maintaining electrical connectivity between die layers.
Solution Approach 2:
The interconnection structure is segmented into multiple components: a through-hole providing vertical alignment, side-wall conductive structures providing lateral connectivity, and bonding pads on adjacent dies. This segmentation allows the interconnection function to be distributed across multiple elements, reducing the required footprint compared to a single large TSV.
2Reliability
If TSVs are used for interconnections, then vertical connectivity is provided, but placement flexibility of IP cores is restricted due to keep-out zones
Solution Approach 1:
The invention changes the interconnection paradigm from vertical TSVs to lateral side-wall connections. This dimensional change removes the vertical keep-out zones that constrain IP core placement, allowing greater flexibility in positioning IP cores on adjacent dies while maintaining vertical connectivity through the side-wall bonding mechanism.
3Area of stationary object
If side wall interconnections are implemented, then chip footprint is reduced, but manufacturing complexity increases
Solution Approach 1:
The side-wall conductive structures are formed on the first die before bonding to the second die. This preliminary formation of conductive structures on the side walls allows for optimized manufacturing sequencing, where the interconnection elements are prepared in advance, reducing the overall manufacturing complexity despite the novel structure.
4Reliability
If conventional TSV interconnections are used, then interconnection reliability is achieved, but space utilization efficiency decreases
Solution Approach 1:
By transitioning from volume-based TSV interconnections to surface-based side-wall interconnections, the patent achieves comparable interconnection reliability with significantly improved space utilization. The lateral conductive structures on side walls utilize the vertical dimension for routing while minimizing footprint, thereby enhancing space utilization efficiency.
Data Source
AI summary
Tools and techniques for a semiconductor package providing side wall interconnections are provided. An apparatus includes two or more die layers that are bonded together, the first 3D stacked die package comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes two or more side wall pads, wherein each side wall pad of the two or more side wall pads is coupled to an interconnect of a respective die layer of the two or more die layers.