3D Die Stacking with Wafer-Level Via Reveal
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Solution Overview
Problem
Conventional die stacking techniques require a reconstituted wafer and gap filling processes to reveal through-die-vias, which can adversely affect lower dies in the stack and are inefficient.
Innovation Solution
The method allows for the creation of die stacks where through-die-via reveals can be performed at the wafer level without reconstitution, using a process that includes forming insulating glass layers and annealing to bond conductor structures, and employing dummy components for heat transfer and molding material to encase the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional die stacking techniques are used with reconstituted wafers and gap filling processes, then through-die-vias can be revealed, but the lower dies in the stack are adversely affected and the process is inefficient
Solution Approach 1:
The patent performs through-die-via reveal at the wafer level before die stacking, rather than after individual dies are stacked. This preliminary action allows all dies to be prepared simultaneously with their vias revealed, eliminating the need for gap filling processes that would otherwise be required to protect lower dies during subsequent reveal operations on stacked configurations.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: wafer-level preparation (including via reveal) followed by die stacking. This segmentation allows the reveal process to be performed on flat wafers where access is unrestricted, avoiding the complexity of navigating through stacked die configurations and eliminating adverse effects on lower dies.
2Reliability
If dies are stacked one at a time on the base die, then die-to-die electrical connections can be established, but the manufacturing process becomes complex and time-consuming
Solution Approach 1:
The patent combines multiple die stacking operations into a single wafer-level process. By performing through-die-via reveal and preparing interconnect structures on entire wafers simultaneously, multiple dies can be stacked in parallel rather than sequentially, significantly improving productivity while maintaining reliable electrical connections through the merged process steps.
Solution Approach 2:
The patent transitions from one-dimensional sequential stacking (one die at a time) to a two-dimensional wafer-level parallel processing approach. This dimensional change allows simultaneous preparation and stacking of multiple dies across the wafer surface, dramatically increasing manufacturing efficiency without compromising connection reliability.
3Reliability
If gap filling processes are used to protect lower dies during via reveal, then lower die damage is prevented, but the manufacturing process becomes more complex and less efficient
Solution Approach 1:
The patent performs via reveal as a preliminary action before die stacking, when all dies are still in their wafer configuration and easily accessible. This eliminates the need for gap filling processes entirely, as the reveal is completed beforehand without requiring protective measures during the actual reveal operation on stacked dies.
Solution Approach 2:
The patent extracts the via reveal operation from the die stacking sequence and performs it separately at the wafer level before stacking. This extraction removes the need for complex gap filling processes that would be required if reveal were performed after stacking, simplifying the overall manufacturing process while maintaining die protection through the timing of the operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the need for gap filling and reconstitution, enabling efficient and reliable die stacking with improved heat management and electrical connectivity.
Implementation Method 1
annealing to bond conductor structures of the first semiconductor die and conductor structures of the second semiconductor die
Implementation Method 2
annealing to metallurgically bond conductor structures
Implementation Method 3
molding material to encase the stack
Implementation Method 4
dummy components for heat transfer
Data Source
Figure 1~2
Figure 3~5
Figure 6~9
AI summary
Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die (40) on a second semiconductor die (35) of a first semiconductor wafer (185). The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die (30) of a second semiconductor wafer (205). The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die (25) of a third semiconductor wafer (225).