Solid-State Devices TRIZ Cases

A pre-dopant diffusion bridge links the buried layer and deep well through thick epitaxy, improving high-voltage and low-voltage isolation.

Selective epitaxial overgrowth forms lateral GaN structures on a vertical transistor, cutting wafer bonding, parasitics, size, and cost.

RC snubber elements are built into the semiconductor structure to cut chip area and process cost while keeping resistance and capacitance stable.

A dielectric mask defines micro-LED dimensions without dry etching, reducing sidewall plasma damage while improving brightness and yield.

Stacking ferroelectric and paraelectric dielectric films raises DRAM capacitor capacitance without enlarging device area, improving refresh and yield.

Intercalated amphiphilic ligands form a buffer layer that protects wavelength-converting nanoparticles from thermal stress while preserving stability and efficiency.

A recessed insulator, epitaxial silicon channel, and polarity gate enable reconfigurable FETs on bulk silicon with standard CMOS processing.

An oxygen supply layer cleans electrode residue during etching, lowering switching voltage and leakage while protecting the Low-k dielectric.

A condensed cyclic emitter reduces steric hindrance and improves resonance and reverse intersystem crossing for lower-voltage, longer-life OLEDs.

Semipolar pit facets let micro-LED active layers avoid etched sidewall defects and internal fields, improving quantum efficiency and wavelength range.

Band-shaped contact holes connect adjacent pillar SRAM regions in one lithography and RIE step, easing alignment limits while preserving dense layouts.

A multilayer hard mask enables deep, narrow CIS isolation implantation while preventing photoresist backflow and preserving straight profiles.

Multiple ring topologies and handshake links let stacked processor-memory units run parallel ML tasks without TSV communication bottlenecks.

Relocating transistors into unused spaces above and below adjacent standard cells narrows cell pitch and reduces IC footprint.

Liner- and mask-formed spacers isolate deep trench fins, remove poly fences, and ease overlay control for denser semiconductor layouts.

A copper deep trench isolation stack reflects NIR radiation back to photodiodes, reducing crosstalk and improving image sensitivity.

Multiple pad layers across different wiring depths maintain chip-to-chip contact strength when uneven substrate thickness changes crimping pressure.

Asymmetric APD region and electrode layout improves charge guidance under a shared microlens, boosting sensitivity and reducing timing jitter.

A stepped active-area layout and optimized gate overlap cut 6T SRAM standby leakage while preserving read stability and process compatibility.

A shifted light-shielding aperture layout redirects large-angle light outside the visible range to limit color deviation without harming fingerprint sensing.

Internal laser-formed cracks guide back grinding to separate chip edges with less thermal damage and preserved flexural strength.

Single-mask patterning forms TFT regions and electrode layouts with reliable gate-channel overlap, cutting display panel mask cost.

A light-transmissive support member and opened connection layer reduce thermal expansion shift at the Mg2Si photodiode-ROIC interface.

A multilayer side electrode and insulating layer help micro-LEDs preserve emission quality while improving fluid-based display assembly.

Plasmon-diffracted light extends the optical path in CMOS pixels, boosting near-infrared absorption without thicker silicon.

A rigid insulating film penetrating low-k insulation helps stacked photodetector pads bond reliably while keeping parasitic capacitance low.

Convex and concave electrode regions create discrete placement sites that reduce unarranged light emitting elements and improve display emission efficiency.

Segmented islands, bridges, and dual wiring layers distribute stress to keep stretchable display connections intact during repeated deformation.

Ion-implanted isolation separates micro-LED mesas without etching, improving substrate adhesion and reducing sidewall damage.

Integrated filling portions and microlenses improve phase difference detection by reducing light loss and reflections in autofocus image sensors.

Sidewall protrusions joined to support patterns stabilize narrow lower electrodes, enabling denser semiconductor arrays and cleaner etching.

Offset pad areas and stacked gate electrodes raise storage density while easing contact alignment in 3D semiconductor memory.

Differential timing on inter-stack word lines equalizes 3D NAND channel potentials, preventing hot carrier injection and data-state distortion.

A silicon-based composite substrate enables InGaAs detector growth and wafer-to-wafer bonding with CMOS ROICs, cutting infrared pixel cost.

A 3D stacked volatile, interface, and non-volatile memory cell shortens data paths and preserves cache-coherent storage without main board routing.

Capacitance-matched wiring and floating diffusions let dual conversion gain pixels improve low-light depth sensing and dynamic range.

A patterned protection layer around the pixel electrode shields the planarization layer during added film integration, improving display yield.

Multiple sub-staircase portions share levels and use multi-stage lowering to shorten 3D memory staircases and cut fabrication steps.

LED pixel chips integrate photodetection on a transfer substrate, enabling motion sensing and face recognition without separate capture hardware.

A shared selection line drives multiple scan lines to maintain pixel charging, cut power use, and support narrow-bezel displays.

Reflective and protruding optical structures turn wasted lateral Micro-LED emission into forward beams to improve display brightness and cut power use.

A stacked MIM light-blocking structure absorbs stray light in image sensors to cut flare, crosstalk, and dark level degradation.

A surrounding light absorber blocks re-reflected light from under-display camera parts, reducing image overlap and visual noise.

Layered partitions and auxiliary layers absorb oblique light so the display panel emits mainly vertical light for clearer viewing angles.

Angled light extraction routes emitted light through conversion layers, improving color conversion and pixel density without thicker films or scattering particles.

A symmetrical multi-well SCR structure boosts failure current and ESD protection in SOI while keeping the protection layout area-efficient.

Recessed and separated pad geometry keeps omitted micro-semiconductor chips from shorting display electrodes while preserving transfer productivity.

Placing silicon and oxide transistor gate electrodes on the same layer cuts masks and process steps while preserving display electrical performance.

Micro-LEDs cure color-conversion fluid inside cover-layer recesses, improving pixel alignment, yield, and throughput for multi-color displays.

A stretchable elastomer stamp picks up multiple LED chips, expands their spacing, and transfers them together to cut micro-LED assembly time and cost.

A halftone mask patterns insulating and semiconductor layers together, cutting mask steps while preserving TFT patterning precision.

A trench-bridged electrode and patterned insulating openings balance current across adjacent LED units while improving light extraction.

Vented UV LED packaging uses UV-opaque shielding to protect epoxy and critical components from UV degradation and extend package life.

A conductive contact layer stabilizes the Schottky barrier during heat treatment, reducing on-current asymmetry in oxide semiconductor memory transistors.

A symmetric widening impurity region builds a stronger potential gradient, improving charge transfer in longer photoelectric conversion sections.

A colored covering member hides electronic parts behind the lens while preserving optical sensor function and uniform light emission.

Square toroidal microlenses focus light onto SPAD active regions without impractical lens thickness, improving detection efficiency and image quality.

Light from carrier recombination reveals charge trapping at the MOSFET interface, enabling in-situ BTI monitoring without interrupting circuitry.

Separate base films and an interposer simplify chip and conductive line layout while keeping display packages compact and signal transmission reliable.

Differential thermal expansion between the package frame and lens holder keeps lens-to-sensor spacing stable and preserves resolution in vehicle imaging.

A protection diode tied through MOL contacts shunts plasma charging and ESD spikes before M1, reducing gate oxide damage in ICs.

Localized elastic patterns, grooves, and filling members relieve curved-area stress in stretchable display interconnects to reduce cracks and extend fatigue life.

Photocured light-absorbing isolation walls and a directional reflecting layer cut LED pixel crosstalk while simplifying fabrication.

A boron and nitrogen bilayer passivates phase change memory sidewalls to block oxidation and preserve switching speed and stability.

Closed curved electrode contacts spread the electric field across mesa arrays, suppressing ESD breakdown without increasing device area.

Direct tungsten deposition on a metal cap removes the gate barrier layer, cutting gate and source/drain contact resistance.

Dual top select gate layers in a 3D NAND stack improve etch uniformity, control threshold voltage, and raise memory density without harder scaling.

A planar coil-and-magnet transformer layout boosts coupling coefficient for cleaner signal transfer while preserving insulation between circuits.

An angled semiconductor channel and ammonia-assisted oxidation improve profile control and widen the process window in high-layer 3D memory fabrication.

Wafer-level through-die-via reveal avoids reconstitution and gap filling, protecting lower dies while improving 3D stack assembly.

A doped p-i-n layer stack with a light-absorbing region and thin contact layer boosts optical conversion while suppressing dark current.

A protective layer shields the DRAM supporting portion edge from oxidation and etching during sacrificial layer removal, preventing collapse and yield loss.

Thermal layers, sensors, and TSVs regulate hot spots in 3D stacked ICs, improving reliability while limiting power density.

Stacked stripe-like active areas and shared gate electrodes raise NAND bit density while easing lithography demands and limiting channel effects.

Magnetic thin-film cores concentrate flux within compact inductors, reducing leakage onto nearby devices without sacrificing energy storage.

Stacked fanout wiring separates data and gate signal lines to shrink the non-display area and enable narrow display borders.

A double-peak hydrogen modifying layer preserves hydrogen through heat treatment, improving epitaxial layer crystallinity and defect passivation.

A segmented SPAD pixel with microlens-guided light and controlled avalanche regions preserves bokeh while enabling phase-difference focus detection.

A thicker pad insulating layer keeps display signal lines covered during etching, preventing short circuits and pad deterioration.

Redefined routing tolerances allow minimum area metal trenches and extended vias to increase chip density without blocking manufacturable interconnects.

Balanced transmission-path capacitance in an anti-serial ESD protector cuts even harmonic distortion and spurious RF emissions.

Selective placement of the organic insulating film cuts light absorption and capacitance, helping polymer liquid crystal displays keep luminance.

Multiple AI processors handle signals from different color filters in parallel, boosting speed while reducing heat and power use.

An amorphous silicon shielding pattern between barrier layers blocks electric-field polarization in the substrate and preserves transistor behavior.

Vertical bitlines across stacked memory dies raise density while improving bandwidth, latency, and rowhammer resilience.

A control node, surrounding detection node, and low-resistance region guide hole current to boost ToF sensitivity and demodulation contrast.

A P-type region blocks N-type diffusion from the backside Si interface, preserving charge pinning and reducing white spots and dark current.

A differentiated trench layout and adjacent p-type region reduce dark current mismatch between effective and OPB pixels, improving black level accuracy.

Parallel oxide-based ReRAM elements with dielectric isolation and individual compliance resistors cut filament variability for dense neuromorphic arrays.

Embedding pillar-based MRAM in a buried power rail brings memory closer to transistors, cutting RC delay while limiting magnetic interference.

Vertical stacking of three micro LED chips with shared electrodes boosts brightness per unit area while reducing chip footprint.

Repositioned pixel switching elements and overlapping storage electrodes cut scan-data intersections, lowering particle-induced shorts and raising panel yield.

Ambient light is detected through color-filtered pixels so exposure and gain can adapt, improving under-screen fingerprint accuracy.

Separating the LED and electronic component regions with raised transmissive encapsulation improves light extraction while keeping the package compact.

Curved-edge subpixel regions let OLED panels raise resolution without destabilizing masks, reducing color mixing and extending panel life.

A low-density photosensitive region and pixel-overlapping signal lines improve light transmittance while enabling narrower bezels.

Surface trench textures redirect longer-wavelength light to increase optical path length, improving IR absorption in thinner silicon imagers.

Varying dielectric thickness raises the drain electrode, easing anode through-hole formation while reducing photoresist use and surface damage.