Silicon-Germanium and Silicon Fin Structures on Bulk Substrate
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Solution Overview
Problem
Semiconductor devices with semiconductor fins on bulk substrates face leakage currents and require insulating material structures, necessitating the formation of semiconductor fins with different materials like silicon-germanium and silicon to optimize performance, particularly for p-type and n-type field effect transistors.
Innovation Solution
A method involving the formation of a stack on a semiconductor substrate with a silicon-germanium alloy layer, a silicon layer, and a second silicon-germanium alloy layer, followed by the creation of semiconductor fins and a shallow trench isolation structure with dielectric spacers to isolate and shape the fins, allowing for the formation of both silicon-germanium and silicon fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor fins are formed on a bulk substrate, then device performance is improved, but leakage currents increase
Solution Approach 1:
The patent segments the semiconductor structure into distinct regions with different materials: silicon-germanium fins for p-type transistors and silicon fins for n-type transistors. This segmentation allows each region to be optimized for its specific transistor type, improving overall device performance while managing leakage currents through material-specific properties
Solution Approach 2:
The patent applies local quality by using different semiconductor materials in different locations on the same substrate. Silicon-germanium is used specifically where p-type transistors are formed, while pure silicon is used for n-type transistors. This localized material selection optimizes electrical properties for each transistor type while controlling leakage currents in their respective regions
2Reliability
If different semiconductor materials are used for fins, then electrical properties are optimized for specific transistor types, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming a uniform silicon-germanium alloy layer across the entire substrate before selectively transforming portions of it. The silicon-germanium layer is first deposited over the whole surface, then selective epitaxial growth or thermal processing is used to convert specific regions to pure silicon. This preliminary uniform deposition simplifies the manufacturing process compared to depositing different materials separately
Solution Approach 2:
The patent utilizes parameter changes by transforming the material composition of the silicon-germanium layer in selective regions. Through controlled thermal processing or epitaxial growth conditions, the germanium concentration is reduced in specific areas to create pure silicon regions. This parameter transformation allows a single deposition step to yield multiple material types, reducing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage currents and enhances the performance of fin field effect transistors by enabling the use of different semiconductor materials on the same substrate, optimizing electrical properties for both p-type and n-type transistors.
Implementation Method 1
The stack and an upper portion of the semiconductor substrate are patterned to form a fin stack structure having a pair of substantially vertical sidewalls
Implementation Method 2
A dielectric spacer that contacts all sidewall surfaces of the silicon-germanium alloy fin is formed. A cavity is formed underneath the silicon portion by removing the silicon-germanium alloy portion selective to the silicon portion while the dielectric spacer prevents etching of the silicon-germanium alloy fin
Implementation Method 3
A cavity is formed underneath the silicon portion by removing the silicon-germanium alloy portion selective to the silicon portion
Data Source
AI summary
A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin.