3D NAND Word Line Segmentation for Channel Coupling
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Solution Overview
Problem
In three-dimensional NAND type nonvolatile memory devices, the increased integration leads to reduced space between memory cells, causing channel coupling capacitance issues that result in unintended programming of nonselected memory cells during operations like programming and reading.
Innovation Solution
The implementation of first and second word lines at each layer, allowing for the application of different voltages to prevent unwanted programming and reading errors by mitigating channel coupling capacitance effects, with word lines being alternately connected through first and second connection lines to maintain distinct voltage levels across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a three-dimensional structure with increased integration, then storage capacity and integration density are improved, but channel coupling capacitance increases causing unintended programming and reading errors
Solution Approach 1:
The patent divides the word lines into two separate sets: first word lines (WL0, WL2, WL4, etc.) and second word lines (WL1, WL3, WL5, etc.). Each set is independently connected through separate connection lines to word line stacks at different locations. This segmentation allows independent voltage control of adjacent memory cells, preventing channel coupling capacitance from causing unintended programming or reading errors while maintaining high integration density.
2Device complexity
If word lines are connected in a conventional single-layer manner, then device complexity is reduced, but channel coupling capacitance causes reading errors and unintended programming
Solution Approach 1:
The patent transitions from a conventional single-layer word line connection to a two-dimensional arrangement with first and second connection lines connecting word lines at different lateral positions. First connection lines connect first word lines to first word line stacks, while second connection lines connect second word lines to second word line stacks. This dimensional separation eliminates channel coupling interference while maintaining manageable device complexity.
Data Source
AI summary
A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.