Backside Contact MRAM Embedded in Buried Power Rails to Cut RC Delay
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Solution Overview
Problem
In semiconductor device design, existing technologies face challenges in integrating pillar-based memory (MRAM) close to transistors to minimize RC delay for last level cache applications, particularly at technology nodes like 14 nm and below, where MRAM is often placed far from transistors and not directly connected to backside contacts, leading to integration issues and increased RC delay.
Innovation Solution
The integration of a pillar-based MRAM device within a buried power rail and backside power distribution network, where a contact via couples front-end of line transistors to the backside power rail, and a non-magnetic conductive spacer is used between the MRAM device and the via to avoid magnetic field interference, allowing direct connection of the MRAM device to the backside contact of the transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If MRAM device is integrated with TSV and placed far apart from transistors, then manufacturing complexity is reduced, but RC delay increases
Solution Approach 1:
The patent moves the MRAM device from traditional planar integration to vertical integration by embedding it within the backside contact via structure. This dimensional transition allows the MRAM to be positioned directly beneath the transistor contact, dramatically reducing the horizontal distance and RC delay while maintaining manufacturing feasibility through vertical stacking rather than lateral expansion.
Solution Approach 2:
The MRAM device is nested within the backside contact via structure, effectively placing one component inside another. The via structure that normally serves only as a conductive pathway is repurposed to house the MRAM cell, eliminating the need for separate dedicated space and reducing overall device footprint while minimizing distance to the transistor.
2Speed
If MRAM is placed close to transistors to minimize RC delay, then speed performance improves, but manufacturing precision requirements increase
Solution Approach 1:
Sacrificial placeholder structures are formed during the transistor fabrication process at predetermined locations where backside contacts will eventually be placed. These placeholders are created before the actual contact formation, establishing precise alignment references that guide subsequent MRAM integration steps and ensure accurate positioning without requiring high-precision alignment between separately fabricated components.
Solution Approach 2:
The sacrificial placeholder acts as an intermediary structure that mediates between the transistor fabrication process and the MRAM integration process. It provides a temporary reference structure that simplifies alignment requirements, allowing the MRAM to be precisely positioned relative to the transistor through the placeholder's predetermined location rather than requiring direct high-precision alignment between the two distinct components.
3Adaptability or versatility
If additional space is allocated for MRAM integration, then device placement flexibility increases, but area utilization decreases
Solution Approach 1:
The backside contact via structure is given multiple functions: it serves as the electrical connection pathway for the transistor and simultaneously houses the MRAM device. This multi-functionality eliminates the need for separate dedicated space for MRAM integration, allowing the same physical structure to fulfill both contact and memory functions, thereby maximizing area utilization while maintaining placement flexibility.
Solution Approach 2:
The patent merges the backside contact structure with the MRAM device housing into a single integrated structure. Instead of having separate contact vias and separate MRAM cells occupying distinct spaces, the MRAM is embedded within the contact via itself, combining two previously separate functional elements into one unified structure that conserves chip area.
4Loss of time
If MRAM is directly connected to backside contact, then RC delay is minimized, but magnetic field interference risk increases
Solution Approach 1:
A non-magnetic conductive spacer is introduced as an intermediary layer between the MRAM device and the backside contact via. This spacer acts as a magnetic field barrier that blocks magnetic flux from reaching the via structure, preventing magnetic interference while maintaining electrical connectivity. The spacer is positioned at the interface where magnetic field leakage would normally occur, effectively decoupling the magnetic components from the conductive pathway.
Solution Approach 2:
The potential harmful effect of magnetic field leakage from the MRAM is converted into a beneficial design feature by intentionally inserting a non-magnetic spacer. This spacer, which might seem like an unnecessary addition that increases complexity, actually serves to contain and control the magnetic field, preventing it from interfering with adjacent structures while allowing the direct connection that minimizes RC delay.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution minimizes RC delay by placing MRAM close to transistors, enabling high-performance integration at advanced technology nodes without requiring additional space, and avoids interference issues by using a non-magnetic spacer, thus improving yield and efficiency.
Implementation Method 1
utilizing a non-magnetic conductive spacer to minimize magnetic interference
Implementation Method 2
minimize RC delay for last level cache applications
Data Source
AI summary
An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.