6T SRAM Cell Layout for Lower Standby Leakage
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Solution Overview
Problem
SRAM cells face challenges in minimizing standby leakage current (Isb) due to process variations and shrinking device sizes, particularly in 6T storage cells, which affects power consumption and access speed, especially during read operations.
Innovation Solution
The design involves a 6T SRAM bit cell structure with a unique active area configuration, including stem, wing, and tooth portions, where the overlap between the gate electrode and active area is optimized to reduce junction and gate leakage, and the butted contact is strategically positioned to minimize leakage paths, allowing for a reduced overlap region and increased distance from isolation features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the overlap region between gate electrode and active area is reduced to minimize leakage, then standby leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
A mandrel structure is introduced as an intermediary element during the fabrication process. The mandrel serves as a temporary structure that defines the active area boundaries, allowing the gate electrode to be precisely positioned relative to the active area through alignment with the mandrel rather than direct alignment between gate and active area. After fabrication, the mandrel is removed. This intermediary structure reduces the direct alignment precision requirements while achieving the desired small overlap region to minimize leakage current.
2Productivity
If device size is shrunk to increase integration density, then productivity is improved, but standby leakage current increases due to process variations
Solution Approach 1:
The patent applies different structural configurations to different parts of the device. Specifically, the active area is designed with a reduced overlap region with the gate electrode in critical areas where leakage occurs, while other regions maintain standard dimensions. This local optimization allows the device to achieve high integration density through size reduction while simultaneously minimizing standby leakage current through localized structural modifications in the overlap region.
3Object-generated harmful factors
If the distance from butted contact to isolation feature is increased to reduce leakage paths, then standby leakage current is reduced, but area of the bit cell increases
Solution Approach 1:
The patent optimizes the spatial arrangement of the butted contact and isolation feature by utilizing vertical positioning and angular orientation rather than simply increasing horizontal distance. The butted contact is positioned to approach the isolation feature at an optimized angle and vertical level, reducing the effective leakage path length without requiring increased horizontal separation. This dimensional optimization allows maintaining small bit cell area while still reducing leakage current through the isolation feature.
Data Source
AI summary
An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.