3D Memory Stack Contact Layout for Higher Storage Density
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing data storage capacity, necessitating innovative approaches to enhance integration and storage efficiency.
Innovation Solution
The semiconductor device incorporates a three-dimensional arrangement of memory cells, featuring stacked gate electrodes, channel structures, and contact plugs, with specific pad and dummy areas configurations to optimize interconnection and storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged two-dimensionally, then the device structure is simple and easy to manufacture, but the data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple layers of gate electrodes, channel structures, and contact plugs are stacked vertically to increase storage capacity while maintaining a compact footprint on the substrate.
Solution Approach 2:
The patent implements nested structures where contact plugs penetrate through multiple stacked layers of gate electrodes and interlayer insulating layers. The channel structures are positioned within the stack, surrounded by gate electrodes on multiple levels, creating a nested configuration that maximizes space utilization.
2Quantity of substance
If gate electrodes are stacked vertically to increase storage density, then data storage capacity increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent forms interlayer insulating layers between stacked gate electrodes that extend beyond the gate electrode edges. These insulating layers are prepared in advance to provide alignment tolerance and prevent short circuits between adjacent gate electrodes during the stacking process.
Solution Approach 2:
The interlayer insulating layers act as intermediary elements between stacked gate electrodes, providing both electrical isolation and mechanical alignment reference. The insulating layers extend beyond the gate electrodes to serve as alignment guides during subsequent manufacturing steps.
3Productivity
If contact plugs are positioned to connect multiple stacked gate electrodes, then interconnection efficiency improves, but the device complexity increases
Solution Approach 1:
The patent divides the interconnection structure into segmented contact plugs, where each contact plug is positioned to connect to specific gate electrodes at different levels. The contact plugs are distributed throughout the stack rather than forming a single complex interconnection system.
Solution Approach 2:
The interlayer insulating layers serve multiple functions: they provide electrical isolation between gate electrodes, act as alignment references for subsequent layers, and facilitate the positioning of contact plugs. This multi-functionality reduces the need for additional specialized structures.
Data Source
AI summary
A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.


