3D Memory Channel Profile Control With Angled Semiconductor Structure
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Solution Overview
Problem
As 3D memory devices approach their scaling limits, traditional planar fabrication techniques become challenging and costly, and controlling the channel profile becomes increasingly difficult with the increasing number of memory layers.
Innovation Solution
A 3D memory device is designed with a stack structure of interleaved conductive and dielectric layers, featuring a channel structure with an angled semiconductor channel and a memory film, where the channel width varies along its length, and a method involving polysilicon layers and ammonia treatment to form a dielectric layer on the channel's sidewalls, allowing for precise control of the channel profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication process, then memory density is improved, but planar process and fabrication techniques become challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory structure with vertical channel holes penetrating through stacked dielectric and conductive layers. This dimensional change enables continued memory density improvement without further scaling planar features, avoiding the fabrication challenges and costs associated with sub-lower-limit planar scaling
2Quantity of substance
If the number of 3D memory layers continues to increase, then memory density is improved, but control of channel profile becomes more and more difficult
Solution Approach 1:
The patent applies different materials with distinct etch selectivities to different regions: doped polysilicon layers are selectively removed after channel hole formation, while undoped polysilicon layers remain to form the final channel structure. This local material differentiation enables precise channel profile control even as the number of memory layers increases
Solution Approach 2:
The patent utilizes ammonia treatment to modify the chemical properties of polysilicon layers, creating different oxidation and etch rates between treated and untreated regions. This parameter change enables selective removal of sacrificial layers while preserving the channel-forming polysilicon, maintaining manufacturing precision across multiple 3D memory layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the control of the channel profile and improves the process window for forming 3D memory devices, overcoming the limitations of traditional planar techniques and enabling more efficient memory density without the cost and complexity of advanced fabrication methods.
Implementation Method 1
a top surface of the second polysilicon layer is ammonia (NH3) treated
Implementation Method 2
An oxidation operation is performed to form a fifth dielectric layer on the first polysilicon layer and the second polysilicon layer exposed by sidewalls of the channel hole
Data Source
AI summary
A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.