SRAM Anti-Fuse Memory Circuit for Soft Error Fixing
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Solution Overview
Problem
Conventional SRAM cells in FPGAs are volatile, prone to soft errors due to noise, and difficult to implement error correction, while nonvolatile memory solutions are slower and more costly, requiring additional power supplies and manufacturing processes.
Innovation Solution
A memory circuit using p-channel and n-channel MOS transistors with thicker gate insulating films as anti-fuses, allowing for a simple and compact configuration that fixes SRAM cell values by selectively breaking the gate insulating film, enabling reliable data storage without the need for multiple power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SRAM cells are used for configuration memory, then the memory values can be easily rewritten and formed by standard CMOS process, but the memory values are volatile and prone to soft errors
Solution Approach 1:
The configuration memory is divided into two functional parts: SRAM cells for temporary storage and anti-fuse elements for permanent fixation. The anti-fuse element is segmented into a first anti-fuse element connected to one inverter and a second anti-fuse element connected to the other inverter, allowing selective fixation of memory values while maintaining rewriteability during programming
Solution Approach 2:
During the programming phase, the anti-fuse elements are prepared by applying high voltage to break down the insulating film, creating a permanent conductive path. This preliminary action fixes the memory value before normal operation, preventing soft errors while maintaining standard CMOS compatibility
2Reliability
If nonvolatile memory is used for configuration memory, then soft errors are prevented, but the operation speed decreases and development time and costs increase
Solution Approach 1:
The anti-fuse elements provide permanent, nonvolatile storage characteristics locally at critical configuration bits, while the overall memory structure maintains SRAM-like speed characteristics. The gate insulating film thickness is locally increased in the anti-fuse region to enable breakdown and permanent storage, while other parts maintain standard SRAM structure for fast operation
3Reliability
If floating gate type memory transistors are added to SRAM cell, then nonvolatile storage is achieved, but additional power supplies and control systems are needed
Solution Approach 1:
The invention extracts the nonvolatile storage function from complex floating gate transistors and implements it using simpler anti-fuse elements connected to standard SRAM inverters. This removes the need for additional power supplies and control systems while achieving permanent storage. The anti-fuse element is a passive structure that requires no active control during normal operation
Solution Approach 2:
The anti-fuse element uses a disposable breakdown mechanism where the gate insulating film is permanently damaged to create a conductive path. This one-time programming approach is simpler and more reliable than reversible floating gate mechanisms, eliminating the need for complex power management during programming
4Reliability
If the gate insulating film is made thicker to prevent soft errors, then noise immunity improves, but the area occupied by the transistor increases
Solution Approach 1:
The transistor population is segmented into two groups: transistors with thicker gate insulating films (anti-fuse elements) for noise immunity and permanent storage, and transistors with standard thickness for normal SRAM operation. This segmentation allows the thicker film transistors to be used only where permanent storage is needed, minimizing area overhead
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a reliable and efficient method for fixing SRAM cell values, reducing the risk of soft errors and manufacturing costs, while maintaining a standard CMOS process compatibility.
Implementation Method 1
a gate insulating film of a transistor or a capacitor to be broken so as to fix a value of the SRAM cell by using an anti-fuse element
Data Source
AI summary
A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.