CIS Isolation Region Hard Mask for High-Aspect-Ratio Implantation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is creating a high aspect ratio isolation region in CMOS Image Sensors (CIS) devices, where the critical dimension of the isolation region is small, and the depth-to-width ratio of ion implantation processes is high, leading to issues with photolithography process capability and photoresist backflow, which can result in failed pixel cell isolation due to the strong penetration of boron ions and the requirement for a precise hard mask.
Innovation Solution
A method involving the formation of a block layer and a hard mask layer on a substrate, followed by photolithography and etching processes to define isolation region patterns, and subsequent ion implantation to create an isolation region, with specific processes including CMP, LPCVD, and CVD to achieve the required depth-to-width ratio and prevent photoresist backflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the critical dimension of the isolation region is reduced to accommodate smaller pixel cells, then the pixel cell size decreases, but the depth-to-width ratio becomes larger making the high aspect ratio process more difficult
Solution Approach 1:
The patent divides the mask structure into multiple layers: a first mask layer (photoresist) and a second mask layer (hard mask). This segmentation allows the photoresist to define the pattern while the hard mask provides the structural support needed for high aspect ratio ion implantation, resolving the contradiction between small pixel size and manufacturable depth-to-width ratio
Solution Approach 2:
The patent adds a vertical dimension to the mask structure by forming a thick hard mask layer beneath the photoresist layer. This multi-layer vertical structure enables the ion implantation to achieve the required depth while maintaining pattern fidelity, effectively managing the depth-to-width ratio challenge in the vertical dimension
2Use of energy by moving object
If boron ion high-energy implantation is used for ion implantation processes, then the penetration capability increases, but the hard mask must meet stricter depth-to-width ratio requirements
Solution Approach 1:
The patent uses a composite mask structure combining photoresist material and hard mask material. The photoresist provides pattern definition capability while the hard mask (typically silicon nitride or similar) provides the mechanical strength and aspect ratio tolerance needed for high-energy ion implantation, allowing both high penetration and strict ratio compliance
3Manufacturing precision
If the photoresist thickness is increased to match the critical dimension requirements, then the pattern definition improves, but photoresist backflow occurs due to surface tension
Solution Approach 1:
The patent introduces a DARC (dielectric anti-reflective coating) layer as an intermediary between the photoresist and hard mask. This layer prevents photoresist backflow by providing a release surface that reduces adhesion, while also serving as an etch stop and reflection prevention layer, thus eliminating the harmful backflow effect without compromising pattern definition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively forms a semiconductor device structure with a high aspect ratio isolation region, meeting the requirements for small-size CIS devices by ensuring straight profiles and appropriate depth-to-width ratios, thereby enhancing the ion implantation process and preventing photoresist backflow.
Implementation Method 1
performing an ion implantation process to form an isolation region in the substrate corresponding to the isolation region pattern
Implementation Method 2
performing a CMP process to the substrate, wherein the CMP process ends when the thickness of the oxides on the surface of an active region reaches a predetermined value
Implementation Method 3
performing a CVD process to form the hard mask layer on the surface of the block layer
Implementation Method 4
depositing silicon nitride to form the block layer, wherein the depositing is performed via an LPCVD process
Data Source
AI summary
A method for making an isolation region of a CIS device includes: forming a block layer on a substrate, below the block layer being an oxide layer, below the oxide layer being a silicon nitride layer, and a shallow trench isolation being formed in the substrate; forming a hard mask layer on the surface of the block layer, the material of the hard mask layer is oxide; performing a photolithography process and an etching process to form an isolation region pattern in the hard mask layer; performing an ion implantation process to form an isolation region in the substrate corresponding to the isolation region pattern.