Semiconductor Chip Pad Layer Layout for Uneven-Thickness Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to suppress faulty electrical connections between semiconductor chips when one chip is crimped onto another, especially when the substrate of the second chip has an uneven thickness, leading to variations in pressing force and potential connection strength.
Innovation Solution
A semiconductor device design featuring a first chip with multiple pad layers in different wiring layers and a second chip with conductive portions, where the pad layers are positioned to evenly distribute pressure and ensure consistent connection strength across varying thicknesses, using an anisotropic conductive film to connect the pads and bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If another chip is crimped onto the semiconductor chip, then electrical connection is established, but faulty connections occur when pressing force varies due to uneven substrate thickness
Solution Approach 1:
The pad layers are positioned at different depths corresponding to different thickness regions of the uneven substrate. Each pad layer is strategically located to ensure optimal electrical contact at its specific depth position, allowing the connection structure to adapt to local variations in substrate thickness and maintain reliable electrical connections throughout.
2Ease of manufacture
If the substrate of another chip has uneven thickness, then manufacturing flexibility is improved, but pressing force varies during crimping causing faulty connections
Solution Approach 1:
The solution transitions from a single-plane pad layer to a multi-layer pad structure extending in the depth dimension. By distributing pad layers across multiple wiring layers at different depths, the structure accommodates variations in substrate thickness along the vertical dimension, converting a two-dimensional connection problem into a three-dimensional solution that maintains consistent electrical contact despite thickness variations.
3Reliability
If pad layers are formed in multiple different wiring layers, then connection reliability improves, but device structure becomes more complex
Solution Approach 1:
The multiple wiring layers serving as pad layer locations fulfill dual functions: they provide the necessary depth distribution to accommodate uneven substrate thickness while simultaneously serving as existing conductive pathways in the semiconductor chip structure. This multi-functional use of the wiring layers reduces the need for additional specialized structures, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses faulty connections by ensuring consistent electrical contact between chips, even with uneven thicknesses, by adjusting the position of pad layers based on the thickness distribution of the second chip, thereby maintaining connection strength across different areas.
Implementation Method 1
using an anisotropic conductive film to connect the pads and bumps
Data Source
AI summary
An object is to provide a semiconductor device and an electronic device that can suppress faulty connections between different chips. The semiconductor device includes: a first chip that includes an insulating layer and a plurality of wiring layers having wires formed in the insulating layer; and at least one second chip that is mounted on the first chip and includes a plurality of conductive portions, wherein the first chip includes a plurality of pad layers and connecting structures, each being formed to electrically connect the pad layer and the conductive portion, the plurality of pad layers being formed at least in the plurality of different wiring layers.