3D NAND Stack With Dual TSG Layers for Uniform Etching
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling down due to increasing costs and limitations in memory density, necessitating a transition to three-dimensional (3D) memory architectures to enhance storage capacity.
Innovation Solution
A 3D NAND memory device structure is developed, featuring a stack of alternating insulating and word line layers with multiple top select gate (TSG) layers, including polysilicon TSG layers and tungsten word line layers, which form channel structures extending through the stack to create memory cell strings, allowing for increased density and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling continues, then memory density increases, but manufacturing cost increases and process complexity becomes unmanageable
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking multiple layers vertically. This dimensional change allows continued memory density improvement without further reducing lateral feature sizes, thereby avoiding the associated manufacturing cost increases and process complexity issues
2Quantity of substance
If feature sizes are reduced to increase density, then memory density improves, but process fabrication becomes challenging and costly
Solution Approach 1:
By moving to 3D stacking architecture, the patent achieves higher memory density through vertical layering rather than lateral feature size reduction. This approach maintains larger, more manufacturable feature sizes while still increasing density, thereby reducing fabrication difficulty and associated costs
3Reliability
If single TSG layer is used, then device complexity is low, but etch uniformity and threshold voltage control are insufficient
Solution Approach 1:
The patent divides the single TSG layer into multiple segmented TSG layers (first TSG layer and second TSG layer) with different functions. The first TSG layer serves as etch stop layer for uniform etching, while the second TSG layer provides threshold voltage control, thereby improving reliability without excessive complexity
Solution Approach 2:
The patent implements multi-functionality within the TSG layer structure where the first TSG layer simultaneously serves as etch stop layer and the second TSG layer provides threshold voltage control. This multi-functional design improves etch uniformity and device performance while maintaining reasonable device complexity
Data Source
AI summary
According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.