3D NAND Memory Structure With Shared Gates and Self-Alignment
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Solution Overview
Problem
The rapid scaling of NAND flash memories leads to technical difficulties such as the worsening short-channel and narrow-channel effects, making it challenging to increase bit density and ensure reliability and operating speed, while conventional lithography techniques struggle to keep pace with device miniaturization.
Innovation Solution
A semiconductor memory structure is developed with stacked, stripe-like active areas that share gate electrodes, allowing for increased bit density without relying heavily on micropatterning techniques, and a manufacturing method that forms these structures in self-alignment, reducing the number of lithography steps required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If element dimensions are reduced to increase bit density, then storage capacity increases, but short-channel and narrow-channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D memory cells to three-dimensional stacked memory cells, where multiple active area layers are stacked vertically. This vertical stacking increases bit density without further reducing horizontal element dimensions, thereby avoiding the worsening short-channel and narrow-channel effects that occur with continued scaling.
Solution Approach 2:
The memory structure is divided into multiple stacked layers, with each layer containing active areas and shareable gate electrodes. This segmentation allows the memory to achieve higher density through vertical stacking while maintaining larger, more reliable individual element dimensions in each layer.
2Quantity of substance
If element dimensions are reduced to increase bit density, then storage capacity increases, but lithography techniques cannot keep pace with scaling
Solution Approach 1:
By moving to vertical stacking, the patent achieves density improvement in the vertical dimension rather than continuing to scale in the horizontal dimension. This approach reduces dependence on advanced lithography techniques, as the vertical structures can be formed using existing lithography capabilities combined with selective etching and deposition processes.
Solution Approach 2:
Multiple active area layers are nested vertically, with each layer containing gate electrodes that can be shared between layers. This nested structure allows efficient use of lithography steps, as patterns in upper layers can be aligned with and share structures from lower layers, reducing the total number of lithography operations required.
3Quantity of substance
If more memory layers are stacked to increase bit density, then storage capacity increases, but the number of manufacturing steps increases
Solution Approach 1:
Gate electrodes are designed to be shared between multiple active area layers, allowing a single gate electrode structure to control multiple layers. This multi-functionality reduces the number of manufacturing steps, as gate electrodes for multiple layers can be formed simultaneously rather than requiring separate formation steps for each layer.
Solution Approach 2:
Multiple active area layers are combined into a single stacked structure, with common gate electrodes serving multiple layers. This merging of functions and structures reduces manufacturing complexity compared to forming separate memory structures for each layer, as processing steps can be performed on multiple layers simultaneously.
Data Source
AI summary
A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.