3D Stacked Memory Cell for Cache-Coherent Non-Volatile Storage
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Solution Overview
Problem
Current data storage and retrieval methods require data to be processed through a main board, leading to prolonged data transmission paths, reduced efficiency, and increased risk of data loss, especially when power is off.
Innovation Solution
A non-volatile three-dimensional memory cell is developed, comprising a volatile memory chip, an interface chip, and a non-volatile memory chip connected in a three-dimensional stacked manner through a heterogeneous integrated structure, allowing data to be programmed and read in a cache coherence manner without processing through the main board, thereby shortening the data transmission path and enhancing storage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transmitted through the main board for processing and storage, then data can be stored and retrieved, but the data transmission path is prolonged and transmission time increases
Solution Approach 1:
The system is segmented into distinct functional modules: volatile memory chip for fast storage, non-volatile memory chip for persistent storage, and interface chip for coordination. This segmentation allows parallel operations and eliminates the need for centralized main board processing, thereby reducing transmission time while maintaining reliability
Solution Approach 2:
The patent transitions from a two-dimensional architecture (main board based) to a three-dimensional stacked architecture where memory chips are vertically integrated. This dimensional change shortens physical transmission paths and enables direct communication between memory components, reducing transmission time without compromising data integrity
2Reliability
If data is transmitted to the main board for processing before storage, then data can be stored, but the efficiency of storing and reading data is reduced
Solution Approach 1:
The memory system performs self-service operations where the interface chip directly manages data transfer between volatile and non-volatile memory chips without requiring main board intervention. This autonomous operation eliminates processing bottlenecks and significantly improves storage and retrieval efficiency while maintaining data reliability
3Reliability
If data is transmitted to non-volatile memory when powered off, then data loss is reduced, but the data transmission path is further extended and transmission efficiency is reduced
Solution Approach 1:
The volatile memory chip and non-volatile memory chip are merged into a single stacked memory system with direct inter-chip connections. This integration eliminates the need for separate transmission paths to the main board during power-off events, reducing path complexity while ensuring data is safely transferred to non-volatile storage for loss prevention
Data Source
AI summary
A non-volatile three-dimensional memory cell, a storage method, and a chip assembly are provided. The non-volatile three-dimensional memory cell includes: a volatile memory chip; an interface chip, connected to the volatile memory chip in a three-dimensional stacked manner through a three-dimensional heterogeneous integrated structure; a non-volatile memory chip, connected to at least one of the volatile memory chip and the interface chip in a three-dimensional stacked manner through the three-dimensional heterogeneous integrated structure, and the non-volatile three-dimensional memory cell is formed. The interface chip includes a communication protocol circuit, the data is programed in at least one of the volatile memory chip and the non-volatile memory chip in a cache coherence manner through the communication protocol circuit. The data is read from at least one of the volatile memory chip and the non-volatile memory chip in a cache coherence manner through the communication protocol circuit.