3D NAND Multi-Stack Word Line Timing for Channel Equalization
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Solution Overview
Problem
In 3D NAND flash memory devices, the inter-stack portions in multi-stack memory blocks face challenges in channel potential equalization, leading to hot carrier injection (HCI) due to voltage differences across memory stacks, which can distort threshold voltage states and affect data integrity.
Innovation Solution
A nonvolatile memory device with a multi-stack memory block structure where the control circuit determines specific word lines adjacent to inter-stack portions as inter-stack word lines, and differently controls their operating time points to apply pass or recovery voltages based on channel hole sizes, ensuring channel potential equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory stacks are stacked closely to increase storage capacity, then storage density is improved, but channel potential equalization becomes difficult leading to hot carrier injection
Solution Approach 1:
The patent applies preliminary action by performing channel potential equalization before program or read operations. Specifically, a equalization operation is executed prior to the main operation to adjust channel potentials in advance, preventing hot carrier injection that would occur during subsequent operations. This preliminary equalization ensures reliable data integrity even when memory stacks are closely stacked to increase storage capacity.
2Manufacturing precision
If inter-stack portion length is increased to facilitate manufacturing, then manufacturing precision is improved, but channel potential equalization becomes more difficult
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting word line voltage levels based on their position relative to inter-stack portions. Specifically, word lines adjacent to inter-stack portions are assigned different voltage levels (e.g., higher pass voltages) compared to word lines in memory stack regions. This parameter adjustment compensates for the longer inter-stack portion lengths created during manufacturing, ensuring proper channel potential equalization despite the increased physical distance.
3Reliability
If word lines are controlled with different time points to equalize channel potential, then hot carrier injection is prevented, but operation complexity increases
Solution Approach 1:
The patent applies local quality by implementing differentiated control strategies for different word line regions. Specifically, word lines adjacent to inter-stack portions are controlled with different timing and voltage levels compared to word lines in the middle of memory stacks. The control circuit identifies the position of each word line and applies localized control parameters accordingly, preventing hot carrier injection at critical inter-stack regions while maintaining standard operation in other regions, thus managing complexity through spatial differentiation.
Data Source
AI summary
A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.