Monolithic 1T1R and 1TnR Memory Arrays for Speed-Density Trade-off
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory technologies face challenges in achieving high-speed, high-density, and cost-effective memory solutions, particularly in integrating two-terminal memory devices that offer reduced power consumption and advanced performance characteristics.
Innovation Solution
A monolithic memory device is developed, combining one-transistor, one-resistor (1T1R) memory arrays for high-performance code memory and one-transistor, multiple-resistor (1TnR) memory arrays for high-density storage class memory, both fabricated using metal oxide semiconductor components and sharing common layers to reduce complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If 1T1R memory arrays are used for code memory, then high performance and speed are achieved, but memory density is limited
Solution Approach 1:
The memory device is divided into two distinct memory arrays: a first 1T1R memory array optimized for high-speed code memory operations, and a second 1TnR memory array optimized for high-density storage class memory operations. This segmentation allows each array to be independently optimized for its specific function, resolving the contradiction between speed and density by providing both capabilities in separate segments within the same device.
2Quantity of substance
If 1TnR memory arrays are used for storage class memory, then memory density is improved, but access speed decreases
Solution Approach 1:
The memory device is divided into two distinct memory arrays: a first 1T1R memory array optimized for high-speed code memory operations, and a second 1TnR memory array optimized for high-density storage class memory operations. This segmentation allows each array to be independently optimized for its specific function, resolving the contradiction between speed and density by providing both capabilities in separate segments within the same device.
3Manufacturing precision
If separate manufacturing processes are used for 1T1R and 1TnR arrays, then manufacturing precision is maintained, but device complexity increases
Solution Approach 1:
The patent combines the manufacturing processes for both 1T1R and 1TnR memory arrays into a single integrated fabrication process. Common layers including the substrate, transistor layers, and resistor layers are formed simultaneously for both array types using shared fabrication steps. This merging approach maintains manufacturing precision through standardized processes while reducing device complexity by eliminating the need for separate manufacturing lines and reducing overall process variability.
Data Source
AI summary
Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.