Composite Substrate for Low-Cost InGaAs-CMOS Wafer Bonding
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Solution Overview
Problem
The high cost and limited availability of InP wafers for infrared photodetectors make infrared imaging devices expensive, and existing hybrid bonding techniques are costly and inefficient for integrating InGaAs-based detectors with CMOS ROIC circuitry.
Innovation Solution
A composite substrate technology using a silicon wafer with a release layer and a template layer of dissimilar material, enabling the growth of InGaAs-based detectors on large-diameter silicon wafers, compatible with CMOS circuitry, and allowing for high-throughput wafer-to-wafer bonding to reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If InP wafers are used to build photodetector arrays, then infrared detection performance is achieved, but manufacturing cost increases significantly and wafer size is limited to 4 inches
Solution Approach 1:
The patent introduces a composite substrate structure with a silicon base substrate, release layer, and template layer as an intermediary system. This mediator enables the growth of InGaAs photodetectors on inexpensive 12-inch silicon wafers, achieving both low cost and high performance by decoupling the substrate material from the active detector material.
Solution Approach 2:
The patent changes the material composition parameters by using InGaAs instead of InP for the photodetector layer, and employs a multi-layer composite substrate with specific thicknesses and materials (silicon base, metal oxide release layer, metal template layer). This parameter optimization allows compatibility with CMOS processes and large-wafer fabrication while maintaining detector performance.
2Reliability
If InP wafers are used for photodetectors, then detector functionality is achieved, but wafer size is limited making wafer-to-wafer bonding difficult
Solution Approach 1:
The composite substrate acts as an intermediary that enables size transformation. By growing photodetectors on 12-inch silicon wafers through the template layer, the system bridges the gap between small InP wafer functionality and large silicon wafer area, facilitating standard wafer-to-wafer bonding processes.
Solution Approach 2:
The patent transitions from the constraint of small InP wafer diameter to large silicon wafer diameter by changing the dimensional parameter of the substrate. The multi-layer structure allows the active detector region to be defined by the template layer pattern rather than the substrate size, enabling large-area fabrication.
3Adaptability or versatility
If hybrid bonding is used to connect photodetectors to CMOS ROIC, then integration is achieved, but manufacturing cost increases and throughput decreases
Solution Approach 1:
The patent changes the integration approach by making the photodetector substrate itself CMOS-compatible through the use of silicon and standard metal layers. This eliminates the need for hybrid bonding and allows direct wafer-to-wafer bonding with CMOS ROIC, dramatically improving throughput and reducing cost while maintaining integration capability.
Data Source
AI summary
A method for forming a composite substrate containing layers of dissimilar materials is provided. The method includes a step of disposing a release layer over a base substrate where the base substrate is composed of a first material. A template layer is attached to the release layer. Characteristically, the template layer is composed of a second material and adapted to form a compound semiconductor device thereon.