Standard Cell Layout With Vertical Transistor Relocation
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the footprint of integrated circuits (ICs) due to limitations in transistor placement and pitch, leading to increased space usage and inefficiencies in chip design.
Innovation Solution
The implementation of an N-PPNN-P dopant-stack architecture and the relocation of transistors to previously empty spaces above and below standard cells, allowing for a narrower standard cell width and increased height without significant disadvantage, thereby reducing the overall footprint of ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistors are placed in conventional locations within standard cells, then transistor placement is straightforward, but the standard cell width increases leading to larger IC footprint
Solution Approach 1:
The patent applies dimensionality change by moving transistors from the conventional horizontal plane within standard cells to vertical spaces above and below the standard cell layer. This allows transistors to be placed in previously unused vertical dimensions, reducing the horizontal footprint of standard cells while maintaining transistor density. The standard cell width is reduced from conventional dimensions to a narrower width, with transistors relocated to vertical regions above and below the standard cell level.
2Area of stationary object
If standard cell width is reduced to decrease IC footprint, then space efficiency improves, but transistor placement becomes more difficult
Solution Approach 1:
The patent resolves this contradiction by transitioning transistor placement from the horizontal dimension to the vertical dimension. Standard cells are narrowed in width, and transistors are relocated to vertical spaces above and below the standard cell layer. This dimensional transition maintains ease of manufacture by using established transistor fabrication processes, while achieving reduced standard cell area and improved space efficiency.
Solution Approach 2:
The patent applies nesting by placing transistors within vertical spaces that are nested above and below the standard cell layer. These vertical regions are essentially empty spaces that are nested within the overall IC structure, allowing transistor integration without increasing the horizontal footprint. The standard cells are nested in a vertical stack configuration with transistors in the upper and lower regions.
Data Source
AI summary
A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.