Dual Conversion Gain Pixel Wiring for Capacitance-Matched Depth Sensing
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Solution Overview
Problem
Current image sensing technologies, particularly those using time-of-flight principles, face challenges in improving low light performance and dynamic range while maintaining efficient depth sensing in bright ambient light conditions.
Innovation Solution
The imaging device incorporates a pixel design with specific wiring patterns and floating diffusion structures that enable dual conversion gain modes, capacitance matching, and symmetrical wiring layouts to enhance charge transfer and storage, thereby improving low light performance and dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single conversion gain mode is used, then device complexity is low, but low light performance and dynamic range are insufficient
Solution Approach 1:
The pixel is divided into multiple floating diffusion regions (first floating diffusion and second floating diffusion) with different capacitance values, enabling dual conversion gain modes within a single pixel structure. This segmentation allows the pixel to handle both low light and bright conditions effectively without requiring multiple separate pixels.
Solution Approach 2:
The pixel dynamically switches between high conversion gain mode (using first floating diffusion with higher capacitance for low light) and low conversion gain mode (using second floating diffusion with lower capacitance for bright conditions) based on ambient light levels. This dynamic adaptation optimizes performance across varying lighting conditions.
2Measurement precision
If capacitance matching is not implemented, then wiring complexity is reduced, but measurement precision of depth information deteriorates
Solution Approach 1:
Different wiring patterns are applied to different floating diffusion regions based on their specific capacitance requirements. The first wiring connected to the first floating diffusion has a pattern optimized for high capacitance, while the second wiring connected to the second floating diffusion has a pattern optimized for low capacitance, achieving local optimization for each region.
Solution Approach 2:
The wiring structures are designed asymmetrically to match the asymmetric capacitance requirements of the two floating diffusion regions. The first wiring and second wiring have different patterns and configurations that correspond to the different capacitance values, enabling precise charge transfer for depth sensing.
3Area of stationary object
If pixel footprint is reduced, then area efficiency improves, but charge transfer efficiency may deteriorate
Solution Approach 1:
The wiring structures are nested within the compact pixel area, with the first and second wirings integrated into the pixel footprint without requiring additional external space. This nesting allows efficient charge transfer paths to be contained within the reduced pixel area.
Solution Approach 2:
The wiring patterns utilize vertical stacking and multi-layer configurations to achieve efficient charge transfer within a reduced horizontal footprint. By transitioning to three-dimensional wiring arrangements, the pixel maintains charge transfer efficiency while reducing overall area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the imaging device's ability to capture depth information effectively in both low light and bright conditions, improving conversion gain and reducing the footprint of the pixel while maintaining efficient charge transfer.
Implementation Method 1
a third wiring connected to ground and capacitively coupled with the first wiring and the second wiring
Implementation Method 2
a photoelectric conversion region, a first transfer transistor coupled to the photoelectric conversion region to transfer charge generated by the photoelectric conversion region
Data Source
AI summary
An imaging device includes a pixel including a photoelectric conversion region, a first transfer transistor coupled to the photoelectric conversion region, a first floating diffusion, a second floating diffusion, a second transfer transistor coupled between the first floating diffusion and the second floating diffusion to control access to the second floating diffusion, a third transfer transistor coupled to the photoelectric conversion region, a third floating diffusion coupled, a fourth floating diffusion, and a fourth transfer transistor coupled between the third floating diffusion and the fourth floating diffusion to control access to the fourth floating diffusion. The imaging device includes a first wiring layer including a first wiring connected to the second floating diffusion, a second wiring connected to the fourth floating diffusion, and a third wiring connected to ground and capacitively coupled with the first wiring and the second wiring.