Semipolar Micro-LED Pit Structure for Higher Quantum Efficiency
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Solution Overview
Problem
Micro-LEDs face low internal and external quantum efficiencies due to high defect densities at etched mesa sidewalls, leading to increased non-radiative recombination and reduced efficiency, especially as their size decreases, and internal fields in c-plane grown LEDs cause quantum-confined Stark effects, reducing radiative efficiency.
Innovation Solution
Micro-LEDs with light-emitting layers grown on semipolar facets of pit structures, such as inverted pyramids, are formed to minimize etching-induced defects and internal fields, resulting in higher quantum efficiencies and a larger light-emitting area with lower carrier density and Auger recombination rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If micro-LEDs are etched to reduce size, then device size decreases and packing density increases, but defect density at sidewalls increases and quantum efficiency decreases
Solution Approach 1:
The patent changes the crystal orientation parameter from c-plane to semipolar planes, which fundamentally alters the defect formation characteristics at etched sidewalls. This parameter change allows maintaining high quantum efficiency while achieving small device dimensions, as semipolar facets exhibit lower defect densities compared to c-plane structures when etched.
Solution Approach 2:
The patent employs composite material structures including multiple semiconductor layers with different compositions (AlGaN, InGaN, GaN) and doping types (n-type, p-type, undoped). This composite approach enables optimization of each layer's properties to compensate for etching-induced defects and achieve high efficiency in miniaturized devices.
2Ease of manufacture
If c-plane grown LEDs are used, then growth process is straightforward, but quantum-confined Stark effects occur and radiative efficiency decreases
Solution Approach 1:
The patent changes the crystal growth orientation parameter from c-plane to semipolar planes. This parameter change eliminates the strong polarization fields that cause quantum-confined Stark effects in c-plane LEDs, thereby improving radiative efficiency while maintaining controllable growth processes through adjusted epitaxial growth conditions.
3Illumination intensity
If indium concentration in InGaN layers is increased to red-shift emission wavelength, then emission spectrum broadens, but layer quality and reliability decrease
Solution Approach 1:
The patent changes the crystal orientation parameter to semipolar planes, which modifies the strain and defect formation characteristics in InGaN layers. This enables growing high-quality InGaN layers with elevated indium concentrations (up to 30% or higher) that would otherwise be difficult to achieve on c-plane substrates, thereby achieving red-shifted emission while maintaining layer quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances internal quantum efficiency, allows for a red-shift in emission wavelength, and improves the reliability of growing high-quality InGaN layers with increased indium concentration, resulting in higher efficiency and broader emission spectrum.
Implementation Method 1
active layers grown only on sidewalls of the pit structure and configured to emit light
Data Source
AI summary
A light emitting diode includes an n-type semiconductor layer including a pit structure formed therein, active layers grown only on sidewalls of the pit structure and configured to emit light, and a p-type semiconductor layer on the active layers and at least partially in the pit structure. In one embodiment, the pit structure is characterized by a shape of an inverted pyramid. The pit structure is formed in the n-type semiconductor layer by, for example, etching the n-type semiconductor layer using an etch mask layer having apertures with slanted sidewalls, or growing the n-type semiconductor layer on a substrate through a mask layer having an array of apertures.


