Pillar SRAM Contact Layout Using Band-Shaped Contact Holes
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Solution Overview
Problem
The challenge is to further increase the degree of integration and performance of semiconductor devices, particularly in SRAM cell circuits that utilize surrounding gate transistors (SGTs), while facing difficulties in reducing the size of chip components and forming precise contact holes due to the close proximity of semiconductor pillars.
Innovation Solution
A method for producing SRAM cell circuits with SGTs involves forming band-shaped contact holes that overlap impurity layers on adjacent semiconductor pillars, allowing for a single process of lithography and RIE, thereby reducing costs and maintaining high integration density without the need for precise mask alignment, and improving pattern precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the chip is reduced to increase integration density, then the degree of integration is improved, but the distance between contact holes decreases making formation more difficult
Solution Approach 1:
The patent transitions from forming contact holes at discrete points to forming band-shaped contact holes that extend in one dimension. This dimensional change allows contact holes to overlap adjacent semiconductor pillars in plan view, enabling a single lithography and RIE process to form contact holes for multiple pillars simultaneously, thereby maintaining manufacturing precision while achieving higher integration density.
Solution Approach 2:
The patent merges the formation of contact holes for multiple adjacent semiconductor pillars into a single band-shaped contact hole structure. By combining what would traditionally be separate contact hole formation steps into one unified process, the patent reduces the number of lithography and RIE steps required while maintaining the ability to precisely form contact holes for high-density integration.
2Manufacturing precision
If traditional separate contact hole formation processes are used for adjacent pillars, then manufacturing precision can be maintained, but the number of process steps increases and costs rise
Solution Approach 1:
The patent merges multiple contact hole formation operations into a single band-shaped contact hole formation process. This consolidation reduces the number of lithography and RIE steps from multiple separate operations to one unified process, thereby decreasing device complexity and manufacturing costs while preserving contact hole precision through the band-shaped geometry.
Solution Approach 2:
The band-shaped contact hole structure serves multiple functions simultaneously: it provides electrical connection for multiple adjacent semiconductor pillars, acts as a unified masking element for subsequent processing, and enables a single lithography/RIE step to accomplish what would otherwise require multiple separate steps. This multi-functionality reduces overall process complexity.
Data Source
AI summary
In formation of an SRAM cell, a band-shaped contact hole C3 is formed that does not overlap, in plan view. N+ layers 32a, 32c, 32d, and 32f formed on and at outer peripheries of the top portions of Si pillars 6a, 6c, 6d, and 6f, that partly overlaps W layers 33b and 33e on P+ layers 32b and 32e connected to the top portions of Si pillars 6b and 6e, that is connected in both the X direction and the Y direction, and that extends in the Y direction. A power supply wiring metal layer Vdd that connects the P+ layers 32b and 32e through the contact hole C3 is formed. After formation of the power supply wiring metal layer Vdd, a word wiring metal layer WL is formed so as to be orthogonal to the power supply wiring metal layer Vdd in plan view.