Chip Package Light Shielding Layer Design
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Solution Overview
Problem
Existing chip packages with light shielding layers suffer from cracks and voids due to high stress solder resist layers, leading to light leakage and compromised optoelectronic device performance.
Innovation Solution
A chip package design featuring a substrate with an optoelectronic device, a conducting layer, an insulating layer, a light shielding layer with a shielding rate of over 80%, and a conducting bump that collectively cover the substrate's surface, eliminating the need for a high stress solder resist layer and thereby preventing cracks and voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high stress solder resist layer is used in existing chip packages, then electrical connection is achieved, but cracks and voids occur leading to light leakage
Solution Approach 1:
The patent removes the problematic solder resist layer entirely from the structure. Instead of using a solder resist layer that generates stress and causes cracks, the invention directly forms a light shielding layer on the substrate surface, eliminating the source of stress-induced defects while maintaining both electrical and light shielding functions.
Solution Approach 2:
The patent combines the light shielding function and electrical connection function into a single integrated structure. The light shielding layer is formed directly on the substrate and includes openings that expose conducting layers, which are then connected to conducting bumps. This merged structure eliminates the need for separate solder resist layers while achieving both light blocking and electrical connectivity.
2Ease of manufacture
If traditional packaging processes are used, then manufacturing is achieved, but fabrication time and cost are high
Solution Approach 1:
The patent segments the packaging process into distinct functional layers formed through a wafer-scale process: substrate preparation, optoelectronic device formation, conducting layer deposition, light shielding layer formation with openings, and conducting bump attachment. This segmented approach allows each layer to be optimized independently while maintaining overall process efficiency and reducing total fabrication time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures effective light shielding, enhances the reliability and performance of the chip package by preventing light leakage and reducing fabrication costs and time through a wafer-scale packaging process.
Implementation Method 1
a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80%
Data Source
AI summary
An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.