Display Transistor Gate Layout With Shared Electrode Layer

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Solution Overview

Problem

Current display apparatuses face challenges in achieving high-quality images while maintaining cost-effectiveness, particularly in the design and integration of transistors and gate electrodes on different layers, which complicates the manufacturing process and increases costs.

Innovation Solution

The display apparatus incorporates a substrate with both silicon-based and oxide-based transistors, where the gate electrodes of both types are located on the same layer, simplifying the manufacturing process and reducing the number of required masks and steps, thereby lowering costs and improving electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If gate electrodes of silicon-based and oxide-based transistors are located on different layers, then device functionality is achieved, but manufacturing complexity and costs increase

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidtransistor layer structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges the gate electrodes of silicon-based transistors and oxide-based transistors onto the same layer, eliminating the need for separate layer structures. This consolidation reduces the number of manufacturing steps and masks required, directly addressing the contradiction by simplifying the manufacturing process while maintaining the functional integrity of both transistor types.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If gate electrodes are integrated on the same layer, then manufacturing costs and process steps are reduced, but transistor performance must be maintained

Engineering Contradiction:
Improvenumber of masks and stepsVSAvoidelectrical characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by providing different gate insulating layer configurations for silicon-based and oxide-based transistors on the same gate electrode layer. The silicon-based transistor receives a first gate insulating layer with specific properties, while the oxide-based transistor receives a second gate insulating layer with different properties, allowing each transistor type to maintain its optimal electrical characteristics despite sharing the same gate electrode layer.

Inventive Principle:
Principle #3Local quality

3Reliability

If different gate insulating layers are provided for silicon-based and oxide-based transistors, then electrical characteristics are optimized, but process complexity increases

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidgate insulating layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent achieves universality by designing a gate electrode layer that serves both silicon-based and oxide-based transistors simultaneously. The gate electrode structure is configured to provide electrical control for both transistor types through appropriately designed gate insulating layers, reducing overall device complexity while maintaining optimized electrical characteristics for each transistor type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4435862A1Display apparatus
Publication Date: 2024.09.25 SAMSUNG DISPLAY CO LTD
  • EP4435862A1 patent drawingFigure 1
  • EP4435862A1 patent drawingFigure 2
  • EP4435862A1 patent drawingFigure 3

AI summary

A display apparatus (1) includes a substrate (100) including a display area (DA) and a peripheral area (PA) surrounding the display area (DA), a first silicon-based transistor (PT1) located on the substrate (100), and including a first semiconductor layer (PA1) including a silicon semiconductor and a first gate electrode (PG1) insulated from the first semiconductor layer (PA1), a first oxide-based transistor (T1, T4) located on the substrate (100), and including a second semiconductor layer (AO1, AO4) including an oxide semiconductor and a second gate electrode (G1, G4) insulated from the second semiconductor layer (AO1, AO4), and a first gate insulating layer (113) located on the first semiconductor layer (PA1) and the second semiconductor layer (AO1, AO4), wherein the first gate electrode (PG1) and the second gate electrode (G1, G4) are located on the first gate insulating layer (113) and are located on substantially a same layer.