3D Memory Staircase Layout With Sub-Staircase Level Sharing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In three-dimensional nonvolatile memory manufacturing, the staircase structure used to lead out stacked word lines results in a long staircase length, increasing manufacturing complexity and load due to the need for multiple steps to achieve the desired level differences.
Innovation Solution
The semiconductor storage device employs a method where multiple sub-staircase portions are formed on the same level and processed to belong to different levels using a multi-stage lowering technique, allowing for reduced staircase length by optimizing mask pattern alignment and etching margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a traditional staircase structure is used to lead out stacked word lines, then the word lines can be accessed, but the staircase length becomes excessively long requiring multiple manufacturing steps
Solution Approach 1:
The staircase structure is divided into multiple sub-staircase portions, each formed at different locations but belonging to the same level. This segmentation allows the staircase to be constructed in modular units rather than as a single continuous structure, reducing the overall length and simplifying manufacturing.
Solution Approach 2:
The patent transitions from a single-level staircase concept to a multi-level arrangement where multiple sub-staircase portions are distributed across different vertical levels. By utilizing the vertical dimension to distribute staircase portions across multiple levels, the horizontal length is reduced while maintaining functionality.
2Manufacturing precision
If multiple steps are used to achieve desired level differences in the staircase, then proper alignment is achieved, but the manufacturing load and complexity increase
Solution Approach 1:
Mask patterns are designed and prepared in advance with predetermined shapes that define the positions and levels of multiple sub-staircase portions. This preliminary action of creating comprehensive mask patterns before fabrication ensures proper alignment is built into the process design rather than achieved through multiple iterative adjustment steps.
Solution Approach 2:
Multiple sub-staircase portions that would traditionally require separate formation steps are merged into a single manufacturing process by using a unified mask pattern design. The mask pattern simultaneously defines multiple sub-staircase portions at different locations and levels, combining what would be multiple operations into one integrated process step.
Data Source
AI summary
A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.