Display TFT Layer Patterning With a Halftone Mask
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Solution Overview
Problem
The existing display device manufacturing processes require a large number of mask steps, leading to reduced efficiency and increased costs due to the complexity of patterning wirings and insulating layers.
Innovation Solution
A display device is fabricated using a reduced number of masks by employing a halftone mask to pattern the gate insulating layer, semiconductor layer, and insulating layer simultaneously, thereby simplifying the process and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to pattern wirings and insulating layers, then patterning precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines multiple mask processes into a single mask process by forming the gate insulating layer pattern and semiconductor pattern simultaneously using one mask. This merging approach maintains the required patterning precision while significantly reducing the number of separate mask steps needed in the manufacturing process.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it patterns both the gate insulating layer and the semiconductor layer in one operation. This multi-functional approach eliminates the need for separate dedicated masks for each layer, reducing overall process complexity while maintaining precision.
2Manufacturing precision
If multiple mask processes are used to pattern wirings and insulating layers, then patterning precision is improved, but manufacturing time and cost increase
Solution Approach 1:
By merging the patterning of the gate insulating layer and semiconductor layer into a single mask process, the patent reduces the total number of manufacturing steps. This combination maintains the necessary patterning precision while significantly improving manufacturing efficiency by reducing process time and the number of sequential operations required.
3Productivity
If a single mask process is used to pattern multiple layers, then manufacturing efficiency is improved, but patterning precision may be compromised
Solution Approach 1:
The single mask process is designed with segmented functional zones that correspond to different pattern requirements. The mask contains distinct regions for patterning the gate insulating layer and semiconductor layer, each optimized for its specific patterning needs. This segmentation within a unified mask maintains high precision for each layer while achieving the efficiency benefits of a single-process approach.
Data Source
AI summary
A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.