Array Substrate Layout for Easier Anode Through-Hole Formation
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Solution Overview
Problem
In bottom-emission display panels, the thick planarization layer makes it difficult to form through holes for the anode, leading to increased exposure time, photoresist wastage, and surface damage, resulting in lower luminous efficiency and poor display quality due to anode crystallization and thin light-emitting layers.
Innovation Solution
The array substrate design includes dielectric layers with varying thicknesses to raise the drain electrode closer to the surface, reducing the thickness of the planarization layer needed for through holes, using organic silicon glass solutions and half-tone masks to form patterns efficiently, and adjusting passivation and buffer layer thicknesses to facilitate anode connection without damaging the surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a thick planarization layer is used to cover the color resist and passivation layer, then the surface flatness is improved, but the difficulty of forming through holes increases and exposure time is extended
Solution Approach 1:
The patent applies local quality by making the buffer layer thickness non-uniform: thicker in the sub-pixel region (first region) and thinner in the light-emitting region (second region). This localized thickness variation allows the planarization layer to achieve sufficient flatness for through-hole formation while keeping the overall structure optimized for both manufacturing and device performance
Solution Approach 2:
The patent changes the thickness parameter of the buffer layer from uniform to non-uniform. Specifically, the buffer layer thickness in the sub-pixel region is greater than in the light-emitting region, which adjusts the elevation of the drain electrode and modifies the required planarization layer thickness, thereby resolving the contradiction between flatness and through-hole formation difficulty
2Shape
If a thick planarization layer is used, then surface flatness is improved, but photoresist wastage increases and surface damage occurs
Solution Approach 1:
By implementing local quality through non-uniform buffer layer thickness, the patent reduces the planarization layer thickness requirement in the light-emitting region. This localized optimization minimizes photoresist consumption during through-hole formation and reduces the risk of surface damage while maintaining adequate flatness where needed
3Loss of substance
If the planarization layer is made thin to reduce photoresist usage, then photoresist wastage is reduced, but the surface flatness deteriorates making through-hole formation difficult
Solution Approach 1:
The patent resolves this contradiction by applying local quality: the buffer layer is thicker in the sub-pixel region to provide sufficient elevation and flatness for through-hole formation, while being thinner in the light-emitting region to minimize overall planarization layer thickness and photoresist usage. This spatially differentiated approach satisfies both requirements simultaneously
4Reliability
If the anode is formed through thick planarization layer, then proper electrical connection is achieved, but the light-emitting layer becomes thin and luminous efficiency decreases
Solution Approach 1:
The patent changes the buffer layer thickness parameter from uniform to non-uniform, with the thickness in the sub-pixel region being greater than in the light-emitting region. This parameter variation elevates the drain electrode in the sub-pixel region, reducing the required planarization layer thickness and consequently the through-hole thickness, which preserves light-emitting layer thickness and maintains high luminous efficiency while ensuring proper electrical connection
Data Source
AI summary
The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.