3D Memory Stack Layout With Vertical Bitlines for Higher Bandwidth
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Solution Overview
Problem
Current memory technologies face limitations in bandwidth and latency, particularly in stacked memory systems, which hinder the full potential of computation in modern systems, and existing memory organization and design fail to optimize 3D layout and stacking for superior performance and density.
Innovation Solution
The implementation of memory stacks with substantially vertical bitlines and orthogonal or skewed wordlines across multiple memory dies, along with advanced memory controller designs and error correction code support, to enhance memory density, reduce rowhammer vulnerability, and improve access bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are stacked vertically to increase density, then memory density is improved, but bandwidth and latency performance deteriorates due to independent macro organization
Solution Approach 1:
The patent transitions from traditional 2D memory organization to 3D vertical organization by routing bitlines vertically through multiple stacked memory dies. This dimensional change allows memory cells across different tiers to share common bitlines, enabling simultaneous access to multiple tiers and thereby improving bandwidth while maintaining high density.
Solution Approach 2:
The patent implements a unified memory controller that manages multiple memory tiers as a single addressable space rather than independent macros. This multi-functional approach allows the same bitlines to serve multiple tiers simultaneously, enabling the system to achieve both high density through stacking and high performance through unified control.
2Ease of manufacture
If conventional 2D memory organization is used, then design and manufacturing is simpler, but memory density and bandwidth are limited
Solution Approach 1:
The patent extends conventional 2D memory design into the third dimension by stacking multiple memory dies vertically and routing bitlines through the stack. This approach maintains compatibility with existing manufacturing processes while achieving higher density, as each tier can be fabricated using standard processes and then stacked using through-silicon via technology.
3Adaptability or versatility
If memory tiers are treated as independent macros, then each tier can be optimized independently, but overall system performance is suboptimal
Solution Approach 1:
The patent creates a unified memory address space that spans multiple tiers, allowing the memory controller to manage all tiers as a single resource. This enables simultaneous access to multiple tiers through the same bitlines, achieving high overall system performance while still allowing individual tier optimization through the vertical bitline sharing architecture.
Data Source
AI summary
Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory IC die is stacked on the first memory IC die. Bitlines are routed through the first and second IC dies in a substantially vertical orientation. Wordlines within the first memory IC die are oriented orthogonal to the bitlines.