Oxide Semiconductor Memory Transistor Contact Layer for Stable On-Current
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Solution Overview
Problem
Oxide semiconductor transistors used in DRAM memory cells experience on-current asymmetry and fluctuating characteristics due to heat treatment, particularly when subjected to an oxygen-containing atmosphere, leading to unstable performance.
Innovation Solution
Incorporating a conductive contact layer with a higher carrier concentration between the oxide semiconductor channel layer and the upper electrode, which maintains a stable Schottky barrier width even during heat treatment, reducing on-current asymmetry and ensuring stable transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an oxide semiconductor transistor is subjected to heat treatment in an oxygen-containing atmosphere during wiring line formation, then the transistor structure is completed and integrated into the memory device, but the transistor characteristics fluctuate and on-current asymmetry occurs
Solution Approach 1:
A contact layer is introduced as an intermediary between the oxide semiconductor layer and the upper electrode. This contact layer acts as a buffer that protects the oxide semiconductor layer from direct exposure to the oxygen-containing atmosphere during heat treatment, preventing oxygen diffusion into the channel region while still allowing the heat treatment process to proceed for wiring line formation.
Solution Approach 2:
The contact layer is formed in advance before the heat treatment process. By preparing this protective layer beforehand, the oxide semiconductor layer is pre-protected against oxygen diffusion that would occur during subsequent heat treatment, thereby maintaining transistor characteristic stability throughout the manufacturing process.
2Device complexity
If the oxide semiconductor layer is directly contacted with the upper electrode, then the device structure is simplified, but oxygen diffusion during heat treatment causes Schottky barrier width fluctuation and on-current asymmetry
Solution Approach 1:
The contact layer serves as a mediator between the oxide semiconductor layer and the upper electrode. This intermediate layer prevents direct contact and thus blocks the diffusion path for oxygen, maintaining a stable Schottky barrier width at the oxide semiconductor-upper electrode interface even during heat treatment in oxygen-containing atmospheres.
Solution Approach 2:
The contact layer is formed with a composition that is different from both the oxide semiconductor layer and the upper electrode, creating an intermediate structure that copies or bridges the properties of both adjacent layers. This compositional gradient helps maintain stable electrical characteristics while providing physical separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces on-current asymmetry and maintains stable transistor characteristics by maintaining a high carrier concentration in the contact layer, ensuring consistent performance even after heat treatment in an oxygen-containing atmosphere.
Implementation Method 1
maintains a stable Schottky barrier width even during heat treatment
Data Source
AI summary
A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.