Display Panel Layout With Single-Mask TFT and Electrode Patterning

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Solution Overview

Problem

The existing display panel manufacturing process is costly due to the high expense of masks required for forming light emitting and driving elements, necessitating a simplified method that maintains reliability and achieves high resolution.

Innovation Solution

A display panel design featuring a base substrate with transistors and light emitting elements, where the transistors include semiconductor pattern layers and gate electrodes, and a method involving etching steps to form active pattern layers, drains, sources, and gate insulating layers, reducing the need for multiple masks by using a single photoresist layer for patterning and etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple masks are used for forming light emitting and driving elements, then manufacturing precision is improved, but manufacturing cost increases

Engineering Contradiction:
Improveprecision of light emitting and driving element formationVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent combines multiple patterning operations into a single mask step. The pixel electrode pattern and common electrode pattern are formed simultaneously using one mask, eliminating the need for separate masking steps for each electrode type. This merging of operations reduces mask costs while maintaining the precision required for high-resolution display manufacturing.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single mask used in the invention serves multiple functions: it defines both the pixel electrode pattern and the common electrode pattern, and also serves as a reference for subsequent etching steps. This multi-functional mask reduces the total number of masks required in the manufacturing process, directly addressing the cost issue while preserving manufacturing precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of manufacture

If the number of masks is reduced, then manufacturing cost decreases, but manufacturing precision may deteriorate

Engineering Contradiction:
Improvemanufacturing costVSAvoidprecision of light emitting and driving element formation
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent performs preliminary patterning of both electrode patterns before the actual formation of light emitting and driving elements. By establishing the electrode patterns first using a single mask, subsequent etching and material deposition steps can proceed with higher precision, as the foundational patterns are already in place. This preliminary action ensures that reducing mask count does not compromise final manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediate pattern layer that serves as a template for subsequent etching steps. This intermediate layer, formed by the single mask, acts as a mediator that transfers the pattern information to the final electrode structures with high fidelity. The intermediary ensures that even with fewer masks, the precision required for high-resolution displays is maintained through careful pattern transfer.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If a simplified manufacturing process is used, then productivity increases, but reliability may deteriorate

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoiddisplay panel reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent employs self-aligned etching processes where previously formed patterns automatically serve as alignment references for subsequent steps. The pixel electrode pattern and common electrode pattern formed by the single mask automatically align with the light emitting and driving element regions, eliminating the need for complex external alignment procedures. This self-service alignment mechanism maintains reliability while simplifying the process and improving productivity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent optimizes etching parameters and material properties to ensure that the simplified single-mask process produces reliable results. By carefully controlling etch selectivity, deposition conditions, and material characteristics, the process achieves the same reliability as multi-mask approaches despite the reduced process complexity. These parameter changes enable the simplified process to maintain high display panel reliability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the manufacturing process, reduces costs, and enables the production of reliable high-resolution display panels by overlapping gate electrodes with channel regions and forming capacitors, enhancing design margin and efficiency.

Implementation Method 1

forming a first photoresist pattern layer by irradiating a photoresist layer with UV light

Methodology Applied
Scientific EffectPhotolithography: Photopolymerisation

Implementation Method 2

forming a first active pattern layer by etching a first active layer by using the first photoresist pattern layer as a mask

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Data Source

PatentUS20240347542A1Display panel and method of manufacturing the same
Publication Date: 2024.10.17 SAMSUNG DISPLAY CO LTD
  • US20240347542A1 patent drawing
  • US20240347542A1 patent drawing
  • US20240347542A1 patent drawing

AI summary

A display panel includes a base substrate, a first transistor disposed on the base substrate and including a first semiconductor pattern layer and a first gate electrode, and a light emitting element disposed on the first transistor and electrically connected to the first transistor. The first semiconductor pattern layer may include a first active pattern layer disposed on the base substrate, a first drain contacting the first active pattern layer, and a first source contacting the first active pattern layer and spaced apart from the first drain. A first spaced region between the first drain and the first source may be defined as a first channel region of the first active pattern layer, and the first gate electrode may overlap the first channel region.