3D DRAM Memory Cell Layout With Vertical Bit Line Contacts
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the cost and complexity of fine-pattern fabrication, necessitating the development of three-dimensional memory cells to increase density and reduce parasitic capacitance.
Innovation Solution
A semiconductor memory device with vertically oriented bit lines and storage nodes, featuring bit line and storage node side-ohmic contacts that increase contact area, and a method for fabricating these devices with double word lines and capacitors, enhancing memory cell integration and external resistance in three-dimensional DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use finer patterns to increase integration degree, then memory density improves, but fabrication cost and complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell layout to three-dimensional vertically stacked architecture. Memory cells are arranged in multiple layers with bit lines extending vertically, allowing increased memory density without requiring finer lateral patterning. This dimensional change enables higher integration while avoiding the fabrication complexity associated with sub-10nm lateral features.
2Quantity of substance
If two-dimensional semiconductor memory devices use finer patterns to increase integration degree, then memory density improves, but fabrication cost increases
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent achieves higher memory density using existing fabrication capabilities rather than requiring more expensive fine-pattern tools. The vertical bit line structure and layered arrangement enable increased integration degree while maintaining compatibility with current manufacturing processes, thereby reducing fabrication cost.
3Device complexity
If traditional bit line contact structure is used, then device structure is simple, but contact area is limited and external resistance is high
Solution Approach 1:
The bit line contact structure transitions from a single-plane contact to a multi-level three-dimensional configuration. Bit line contact nodes are formed at multiple vertical levels, and bit line side-ohmic contacts extend vertically to connect to these nodes. This vertical stacking increases the total contact area between bit lines and active layer, thereby reducing external resistance while maintaining reasonable structural complexity.
Solution Approach 2:
The patent combines multiple contact functions into an integrated three-dimensional structure. Bit line contact nodes at different levels, bit line side-ohmic contacts, and vertical bit line conduits work together as a unified contact system. This merging of contact elements across multiple dimensions achieves lower external resistance through increased effective contact area while avoiding the need for separate complex contact structures.
Data Source
AI summary
A semiconductor memory device and method for making the same. The semiconductor device includes a transistor laterally extending in a direction parallel to a substrate and including an active layer over the substrate, the active layer having a first end and a second end; bit line contact nodes formed on an upper surface and a lower surface of the first end of the active layer, respectively; a bit line side-ohmic contact vertically extending and connecting to the first end of the active layer and the bit line contact nodes; a bit line extending in a vertical direction to the substrate and connected to the bit line side-ohmic contact; and a capacitor connected to the second end of the active layer.