3D DRAM Cell Layout With Horizontally Offset Capacitor-Transistor Pairs
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Solution Overview
Problem
Existing memory architectures face challenges in achieving high integration levels while maintaining device performance, particularly in dynamic random access memory (DRAM) units, where capacitors and transistors are not optimally integrated.
Innovation Solution
The integration of transistors and capacitors is achieved on a common horizontal level, with capacitors being horizontally offset from transistors, and the devices are vertically stacked, allowing for improved architectural layouts and fabrication methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory architectures are used with separate transistor and capacitor layouts, then fabrication processes are simpler, but integration density and device performance are limited
Solution Approach 1:
The patent transitions from traditional planar layouts to a three-dimensional vertically-stacked architecture where transistors and capacitors are stacked along the vertical dimension while maintaining horizontal offset. This dimensional change enables higher integration density by utilizing the vertical space above the substrate, effectively multiplying the functional area available per unit footprint without increasing planar complexity proportionally.
Solution Approach 2:
The patent implements a nested configuration where the capacitor is positioned vertically above and offset from the transistor, creating a compact integrated structure. The capacitor's bottom electrode is offset horizontally from the transistor's channel region, allowing the capacitor to be nested in the vertical space above the transistor while maintaining electrical isolation and functional independence, thereby increasing integration density.
2Productivity
If capacitors and transistors are vertically stacked with horizontal offset, then integration density improves, but fabrication precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning actions during fabrication where the capacitor electrode patterns are formed with predetermined horizontal offsets relative to the transistor structures. By pre-establishing the offset positions through sequential deposition and patterning steps, the alignment precision requirements are managed through controlled process steps rather than requiring ultra-precise single-step alignment, thus enabling vertical stacking with acceptable manufacturing precision.
3Reliability
If higher integration levels are achieved through vertical stacking, then device performance improves, but process complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct sequential stages: forming transistor structures at the first level, depositing insulative material, forming capacitor electrodes at the second level with horizontal offset, and completing the vertical stack. This segmentation of the complex fabrication process into manageable segments with clear intermediate states reduces overall process complexity while enabling the high-performance vertical stacked architecture.
Data Source
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AI summary
Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.